[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH v9 09/13] xen/arm: smmu-v3: add suspend/resume handlers


  • To: Mykola Kvach <xakep.amatop@xxxxxxxxx>
  • From: Luca Fancellu <Luca.Fancellu@xxxxxxx>
  • Date: Thu, 14 May 2026 16:41:41 +0000
  • Accept-language: en-GB, en-US
  • Arc-authentication-results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 4.158.2.129) smtp.rcpttodomain=gmail.com smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=arm.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dkim=[1,1,header.d=arm.com] dmarc=[1,1,header.from=arm.com])
  • Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none
  • Arc-message-signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=mADvXDcdpVEOIdGT8nopkjibaLkuis7WqzV8jV4RAB8=; b=FVgJpRczaBcWSiSiWvMJVuBFLygp1dLem1YH6NjxKMeetIa28KKNuTLjaaAAWNuKb1Vpd6Qnk4wXpgXqbtzxVNdXVYOpIonDQmAJhsB0421/jXAn29/sXIF8pSqugBdYAIjIqvQWxFpMisx81i/Q1oj/s5XyA1kSaikFx4m9KVFgw1IAOO2zEWFOwWxscykkEJsLKulb+kM/2NlLyTg41wmZA99kpY80wG56yBwg8C3WkFBlZxSUkjNs8H4U2HMUlYD5/bhCCy2XCBprxwMg0YBjADBeiB+dWU7gxBvIa190WcNbX+74z0itoLpzz30ewES7vZ7VkLhz2IUtCZZyEg==
  • Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=mADvXDcdpVEOIdGT8nopkjibaLkuis7WqzV8jV4RAB8=; b=Uys74nfkqK2rRDgP80KT4kbfjm68um/kkFYaWIuwhFLLy773jOGqtZ57XlIjs/5ruoY1pPwFF6pJPwgWu5m8iKuKtYQImSLr4J9GWp3vFlUCnMeOKAsswd86BR2GbqZ+rqQ0rQul0F1nFklixPyfyD4lUH7E3YPZ37FUp6pcml3F/5ZMv8x7UrA63PZINJHFuBQn0csoN34dkOtozlAXhp/AMcZkfTZLgd7mNz6kTxMAnQODOHYMkrrgUx2EbixvKr1/VZK4K4BWqiarj8tbyAbBDZgx19VLcAuReOs74VdwUY5FHlCtcEEkqxh+8ifY8DVGqnbGEhjuoYlfkfptmQ==
  • Arc-seal: i=2; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=pass; b=Sl87ylpzEcS4sMoVjQGrwcKSFlbe5lTwmbzP7YeQQ6sDesGqiddcRi52rYHvUSzHoF5dKrqAZSeYA8L7VspcjWTOeHbp6z+Y9pV99KjUQ2NVrOi00lQyIVVjX28gR4mZtMi6er5BqnXElNXwsA8cHthuwCTsMNgUANBsceF1INZNg8IEwi3ulVBxomKfCappTXuuBCYlW+HqCcmuSNLpcfsQgTgbN6xy5KoZOAfr7Cwbi+wAblj6XsNKVrhwhaAXBoQyHmPS5IWtnYdrrW33wj9IYUpaux8/K8pDB3y3y+M+D61afCvfF4IGX6TBrZGOGcMkF+xsLyUIT/uTLeKqdA==
  • Arc-seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=lin+YFZJJXWn41uKo2v9mHuqSBmbLyVcA0bjbbP7WXGCcWxqMBIXUxRPf8NgWNmoD0gftzm1+KsX1cX5g7LmrJNYv9Oe4AKyY5IU0IWdp+SALEbHxy2uWH8n4RYRS+y/VmElt+3iCbDBUAiMyQNoX8NCSwmTULwtKytILNKo2TIWq09CZ6hf0DI9oEqlm7W1dc7T4r18OMiSJLtLwH0AFF0d09SFeg/TmpXtXAFoBwf6NVRXxkTIrSHl0NCX0NzRgE0ckko8ACJVdLykQ0TzzaGpZP8Bbwzvtud2cCf6ODaukxnbHOB7SF/aHEgnCzADTf/udDpOScAhrPnoTJFePw==
  • Authentication-results: eu.smtp.expurgate.cloud; dkim=pass header.s=selector1 header.d=arm.com header.i="@arm.com" header.h="From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck"; dkim=pass header.s=selector1 header.d=arm.com header.i="@arm.com" header.h="From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck"
  • Authentication-results-original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com;
  • Cc: "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>, Mykola Kvach <mykola_kvach@xxxxxxxx>, Bertrand Marquis <Bertrand.Marquis@xxxxxxx>, Rahul Singh <Rahul.Singh@xxxxxxx>, Stefano Stabellini <sstabellini@xxxxxxxxxx>, Julien Grall <julien@xxxxxxx>, Michal Orzel <michal.orzel@xxxxxxx>, Volodymyr Babchuk <Volodymyr_Babchuk@xxxxxxxx>, Pranjal Shrivastava <praan@xxxxxxxxxx>
  • Delivery-date: Thu, 14 May 2026 16:42:56 +0000
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
  • Nodisclaimer: true
  • Thread-index: AQHc4jI185A+Eexrf0ingdP9c/cyN7YNvIyA
  • Thread-topic: [PATCH v9 09/13] xen/arm: smmu-v3: add suspend/resume handlers

Hi Mykola,

> 
> +static int arm_smmu_enable_irqs(struct arm_smmu_device *smmu)
> +{
> + int ret;
> + u32 irqen_flags = IRQ_CTRL_EVTQ_IRQEN | IRQ_CTRL_GERROR_IRQEN;
> +
> + if ( smmu->features & ARM_SMMU_FEAT_PRI )
> + irqen_flags |= IRQ_CTRL_PRIQ_IRQEN;
> +
> + /* Enable interrupt generation on the SMMU */
> + ret = arm_smmu_write_reg_sync(smmu, irqen_flags,
> +      ARM_SMMU_IRQ_CTRL, ARM_SMMU_IRQ_CTRLACK);
> + if ( ret )
> + {
> + dev_warn(smmu->dev, "failed to enable irqs\n");
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +/*
> + * Probe-time only: request host IRQs and, when available, program the SMMU's
> + * MSI doorbells. Resume does not restore the SMMU *_IRQ_CFGn MSI registers,
> + * so any host suspend support must treat the active MSI IRQ path as
> + * unsupported until that restore path exists.
> + */
> static int __init arm_smmu_setup_irqs(struct arm_smmu_device *smmu)
> {
> int ret, irq;
> - u32 irqen_flags = IRQ_CTRL_EVTQ_IRQEN | IRQ_CTRL_GERROR_IRQEN;
> 
> /* Disable IRQs first */
> ret = arm_smmu_write_reg_sync(smmu, 0, ARM_SMMU_IRQ_CTRL,
> @@ -2028,22 +2052,7 @@ static int __init arm_smmu_setup_irqs(struct 
> arm_smmu_device *smmu)
> }
> }
> 
> - if (smmu->features & ARM_SMMU_FEAT_PRI)
> - irqen_flags |= IRQ_CTRL_PRIQ_IRQEN;
> -
> - /* Enable interrupt generation on the SMMU */
> - ret = arm_smmu_write_reg_sync(smmu, irqen_flags,
> -      ARM_SMMU_IRQ_CTRL, ARM_SMMU_IRQ_CTRLACK);
> - if (ret) {
> - dev_warn(smmu->dev, "failed to enable irqs\n");
> - goto err_free_irqs;
> - }
> -
> return 0;
> -
> -err_free_irqs:
> - arm_smmu_free_irqs(smmu);
> - return ret;
> }
> 
> static int arm_smmu_device_disable(struct arm_smmu_device *smmu)
> @@ -2057,7 +2066,7 @@ static int arm_smmu_device_disable(struct 
> arm_smmu_device *smmu)
> return ret;
> }
> 
> -static int __init arm_smmu_device_reset(struct arm_smmu_device *smmu)
> +static int arm_smmu_device_reset(struct arm_smmu_device *smmu)
> {
> int ret;
> u32 reg, enables;
> @@ -2163,17 +2172,9 @@ static int __init arm_smmu_device_reset(struct 
> arm_smmu_device *smmu)
> }
> }
> 
> - ret = arm_smmu_setup_irqs(smmu);
> - if (ret) {
> - dev_err(smmu->dev, "failed to setup irqs\n");
> + ret = arm_smmu_enable_irqs(smmu);
> + if ( ret )
> return ret;
> - }
> -
> - /* Initialize tasklets for threaded IRQs*/
> - tasklet_init(&smmu->evtq_irq_tasklet, arm_smmu_evtq_tasklet, smmu);
> - tasklet_init(&smmu->priq_irq_tasklet, arm_smmu_priq_tasklet, smmu);
> - tasklet_init(&smmu->combined_irq_tasklet, arm_smmu_combined_irq_tasklet,
> - smmu);
> 
> /* Enable the SMMU interface, or ensure bypass */
> if (disable_bypass) {
> @@ -2181,20 +2182,16 @@ static int __init arm_smmu_device_reset(struct 
> arm_smmu_device *smmu)
> } else {
> ret = arm_smmu_update_gbpa(smmu, 0, GBPA_ABORT);
> if (ret)
> - goto err_free_irqs;
> + return ret;
> }
> ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0,
>      ARM_SMMU_CR0ACK);
> if (ret) {
> dev_err(smmu->dev, "failed to enable SMMU interface\n");
> - goto err_free_irqs;
> + return ret;
> }
> 
> return 0;
> -
> -err_free_irqs:
> - arm_smmu_free_irqs(smmu);
> - return ret;
> }
> 
> static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu)
> @@ -2558,10 +2555,23 @@ static int __init arm_smmu_device_probe(struct 
> platform_device *pdev)
> if (ret)
> goto out_free;
> 
> + ret = arm_smmu_setup_irqs(smmu);
> + if ( ret )
> + {
> + dev_err(smmu->dev, "failed to setup irqs\n");
> + goto out_free;
> + }
> +
> + /* Initialize tasklets for threaded IRQs*/
> + tasklet_init(&smmu->evtq_irq_tasklet, arm_smmu_evtq_tasklet, smmu);
> + tasklet_init(&smmu->priq_irq_tasklet, arm_smmu_priq_tasklet, smmu);
> + tasklet_init(&smmu->combined_irq_tasklet, arm_smmu_combined_irq_tasklet,
> + smmu);
> +
> /* Reset the device */
> ret = arm_smmu_device_reset(smmu);
> if (ret)
> - goto out_free;
> + goto out_free_irqs;
> 
> /*
> * Keep a list of all probed devices. This will be used to query
> @@ -2575,6 +2585,8 @@ static int __init arm_smmu_device_probe(struct 
> platform_device *pdev)
> 
> return 0;
> 
> +out_free_irqs:
> + arm_smmu_free_irqs(smmu);
> 
> out_free:
> arm_smmu_free_structures(smmu);
> @@ -2855,6 +2867,96 @@ static void arm_smmu_iommu_xen_domain_teardown(struct 
> domain *d)
> xfree(xen_domain);
> }
> 
> +#ifdef CONFIG_SYSTEM_SUSPEND
> +
> +static void arm_smmu_reset_for_suspend_rollback(struct arm_smmu_device *smmu)
> +{
> + int ret = arm_smmu_device_reset(smmu);
> +
> + if ( ret )
> + dev_err(smmu->dev, "Failed to reset during suspend rollback: %d\n",
> + ret);
> +}
> +
> +static int arm_smmu_suspend(void)
> +{
> + struct arm_smmu_device *smmu;
> + int ret = 0;
> +
> + list_for_each_entry(smmu, &arm_smmu_devices, devices)
> + {
> + /* Abort all transactions before disable to avoid spurious bypass */
> + ret = arm_smmu_update_gbpa(smmu, GBPA_ABORT, 0);
> + if ( ret )
> + goto fail;

Should we have this here as the restore path calls arm_smmu_enable_irqs()?

ret = arm_smmu_write_reg_sync(smmu, 0,
                              ARM_SMMU_IRQ_CTRL,
                              ARM_SMMU_IRQ_CTRLACK);
if ( ret )
    goto fail;

Cheers,
Luca




 


Rackspace

Lists.xenproject.org is hosted with RackSpace, monitoring our
servers 24x7x365 and backed by RackSpace's Fanatical Support®.