[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH 03/16] x86/intel: Drop the paddr_bits workaround for P4 Nocona/Prescott CPUs
- To: Xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- From: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
- Date: Tue, 27 Jan 2026 13:35:32 +0000
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=citrix.com; dmarc=pass action=none header.from=citrix.com; dkim=pass header.d=citrix.com; arc=none
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=uYu0fLbMD46CRHBOk/DythtbDqFmMQu0j9bHWiw+JnY=; b=u2q0FbTR4O8bSBrNjro0aNgZowR+JL3odjlGA65Vzhn7J+rNqBzscSAa4BNcvjx0g7entvXobkcusjkdtzVObbu6WkSafRxusSH+fUc71z0Nch175AUAemK5+IVL0lhIfJpklAy3RT/Bdi394N/tid255gAAue7pbnp0zl351CrJqcIQlUnS6JokCnj/1b7ijAGpnIqtoQ1NqE9hny4lBBXzIM9GVxBLwXXUlBB775s6GGZDFA2/GqTTkHApKzPYh66xn6spf93ZZLIy6jzPhWeY//pTCal4yQgJrVnSEJq4drR3128GvmQauUxtRpdYj9dtdP2Akgxun3B5Xjtdzg==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=EmqNm7IU6nj0IuoIZWC8J/CxcFw9ewN4iEyZK4D1xCKXBpr0XUxUiMMxt2TwKtSNrSlNtHEr+6Zs7gDkOq1yeGAKhg/pkBKsxbPkanXmP09QpufB+R+2hnIY+5XYjA0C3dr6ggH4qwWd+2A9PwugiPlOnjokYJBp0O5wcb3PqROrBbukZMzqDEQ+Wk85riOXP1Y118OQnsJlz9LNJTnq6KRiM+WdxxcLvhI0sYDe6zgikxJlnGRUyhKZ5hw8VRrzPbs2NcKbFukXHb9+S7rYmHqXS/59tDeX1UJ06aLLlsfE6l1dbZXVhs3Y7WfzJaciwYfnj6hHoXKTh7Q89jmNPw==
- Authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=citrix.com;
- Cc: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Jan Beulich <JBeulich@xxxxxxxx>, Roger Pau Monné <roger.pau@xxxxxxxxxx>, Julian Vetter <julian.vetter@xxxxxxxxxx>, Teddy Astie <teddy.astie@xxxxxxxxxx>, Kevin Lampis <kevin.lampis@xxxxxxxxxx>
- Delivery-date: Tue, 27 Jan 2026 13:35:44 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 26/01/2026 5:53 pm, Andrew Cooper wrote:
> These are 32bit CPUs only. 64bit support started with model 4 (Prescott-256).
It turns out that this isn't true. These CPUs did have Long Mode.
I'll need to rework this patch into a later one.
~Andrew
|
