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Re: [PATCH v2 1/8] arm64: Provide dcache_by_myline_op_nosync helper
- To: Will Deacon <will@xxxxxxxxxx>
- From: Barry Song <21cnbao@xxxxxxxxx>
- Date: Mon, 26 Jan 2026 09:43:02 +0800
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- Delivery-date: Mon, 26 Jan 2026 01:43:46 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
[...]
> > */
> > - .macro dcache_by_myline_op op, domain, start, end, linesz, tmp, fixup
> > + .macro raw_dcache_by_myline_op op, start, end, linesz, tmp, fixup
> > sub \tmp, \linesz, #1
> > bic \start, \start, \tmp
> > .Ldcache_op\@:
> > @@ -402,14 +401,13 @@ alternative_endif
> > add \start, \start, \linesz
> > cmp \start, \end
> > b.lo .Ldcache_op\@
> > - dsb \domain
>
> Naming nit, but I'd prefer this to be dcache_by_myline_op_nosync() for
> consistency with the other macros that you're adding. The 'raw' prefix
> is used by raw_dcache_line_size() to indicate that we're getting the
> value from the underlying hardware register.
Ok. thanks!
>
> >
> > _cond_uaccess_extable .Ldcache_op\@, \fixup
> > .endm
> >
> > /*
> > * Macro to perform a data cache maintenance for the interval
> > - * [start, end)
> > + * [start, end) and wait for completion
> > *
> > * op: operation passed to dc instruction
> > * domain: domain used in dsb instruction
> > @@ -420,7 +418,23 @@ alternative_endif
> > */
> > .macro dcache_by_line_op op, domain, start, end, tmp1, tmp2, fixup
> > dcache_line_size \tmp1, \tmp2
> > - dcache_by_myline_op \op, \domain, \start, \end, \tmp1, \tmp2, \fixup
> > + raw_dcache_by_myline_op \op, \start, \end, \tmp1, \tmp2, \fixup
> > + dsb \domain
> > + .endm
>
> This could just be dcache_by_line_op_nosync() + dsb.
Ok. thanks!
Best Regards
Barry
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