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Re: [PATCH v1 01/15] xen/riscv: introduce struct arch_vcpu


  • To: Jan Beulich <jbeulich@xxxxxxxx>, Oleksii Kurochko <oleksii.kurochko@xxxxxxxxx>
  • From: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
  • Date: Tue, 6 Jan 2026 14:59:59 +0000
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  • Cc: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Alistair Francis <alistair.francis@xxxxxxx>, Bob Eshleman <bobbyeshleman@xxxxxxxxx>, Connor Davis <connojdavis@xxxxxxxxx>, Anthony PERARD <anthony.perard@xxxxxxxxxx>, Michal Orzel <michal.orzel@xxxxxxx>, Julien Grall <julien@xxxxxxx>, Roger Pau Monné <roger.pau@xxxxxxxxxx>, Stefano Stabellini <sstabellini@xxxxxxxxxx>, xen-devel@xxxxxxxxxxxxxxxxxxxx
  • Delivery-date: Tue, 06 Jan 2026 15:00:27 +0000
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>

On 06/01/2026 2:26 pm, Jan Beulich wrote:
> On 06.01.2026 15:19, Oleksii Kurochko wrote:
>>>> +    struct
>>>> +    {
>>>> +        register_t s0;
>>>> +        register_t s1;
>>>> +        register_t s2;
>>>> +        register_t s3;
>>>> +        register_t s4;
>>>> +        register_t s5;
>>>> +        register_t s6;
>>>> +        register_t s7;
>>>> +        register_t s8;
>>>> +        register_t s9;
>>>> +        register_t s10;
>>>> +        register_t s11;
>>>> +
>>>> +        register_t sp;
>>>> +        register_t gp;
>>>> +
>>>> +        /* ra is used to jump to guest when creating new vcpu */
>>>> +        register_t ra;
>>>> +    } xen_saved_context;
>>> The xen_ prefix here also doesn't exist in Arm code.
>> I think it should be added for Arm too. I can send a patch.
> ... this, to reword my comment: What value does the xen_ prefix add?

This was my recommendation after reverse engineering how ARM worked to
explain it to Oleksii.  But I also thought I said to write a real
comment too.

This is arbitrary *Xen* state, not guest state like you'd expect to find
in struct vcpu.  The guest GPR state is at the base of the vCPU stack.

I suggested that this property be made clearer for the benefit of anyone
trying to decipher the context switching logic.

~Andrew



 


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