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Re: [RFC PATCH for-4.22 1/2] x86/platform: Expose DTS sensors MSR
- To: Teddy Astie <teddy.astie@xxxxxxxxxx>
- From: Jan Beulich <jbeulich@xxxxxxxx>
- Date: Tue, 28 Oct 2025 10:22:44 +0100
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- Cc: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Roger Pau Monné <roger.pau@xxxxxxxxxx>, xen-devel@xxxxxxxxxxxxxxxxxxxx
- Delivery-date: Tue, 28 Oct 2025 09:22:51 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 27.10.2025 18:26, Teddy Astie wrote:
> Intel provide CPU sensors through "DTS" MSRs. As there MSR are core-specific
> (or package-specific), we can't reliably fetch them from Dom0 directly.
> Expose these MSR (if supported) through XENPF_resource_op so that it is
> accessible through hypercall.
>
> Suggested-by: Jan Beulich <jbeulich@xxxxxxxx>
> Signed-off-by: Teddy Astie <teddy.astie@xxxxxxxxxx>
> ---
> I'm not a fan of doing a inline cpuid check here, but I don't have a
> better approach in mind.
>
> xen/arch/x86/include/asm/msr-index.h | 2 ++
> xen/arch/x86/platform_hypercall.c | 6 ++++++
> 2 files changed, 8 insertions(+)
>
> diff --git a/xen/arch/x86/include/asm/msr-index.h
> b/xen/arch/x86/include/asm/msr-index.h
> index df52587c85..98dda629e5 100644
> --- a/xen/arch/x86/include/asm/msr-index.h
> +++ b/xen/arch/x86/include/asm/msr-index.h
> @@ -510,6 +510,8 @@
> #define MSR_IA32_THERM_INTERRUPT 0x0000019b
> #define MSR_IA32_THERM_STATUS 0x0000019c
> #define MSR_IA32_MISC_ENABLE 0x000001a0
> +#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2
> +#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1
> #define MSR_IA32_MISC_ENABLE_FAST_STRING (1<<0)
> #define MSR_IA32_MISC_ENABLE_PERF_AVAIL (1<<7)
> #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1<<11)
Now new additions like this to this file please (and even less so ones
disagreeing in padding with adjacent lines). Please go find this comment
in the file:
/*
* Legacy MSR constants in need of cleanup. No new MSRs below this comment.
*/
Jan
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