[PATCH] x86/MCE: adjust S3 resume handling

[Jan Beulich <jbeulich@xxxxxxxx>]

The BSP resume path calls mcheck_init() with the address of
boot_cpu_data, thus rendering comparisons against that pointer
ineffective. The additional "bsp" boolean needs to be used (and
propagated as necessary) instead.

While touching intel_init_thermal(), constify its 1st parameter, which
in turn requires touching intel_thermal_supported() as well.

Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
---
While I'm pretty sure about the change for the first of the printk()s in
intel_init_thermal(), the 2nd one there is less clear. IOW there could
be an argument for keeping the conditional as is there.

--- a/xen/arch/x86/cpu/mcheck/mce_amd.c
+++ b/xen/arch/x86/cpu/mcheck/mce_amd.c
@@ -318,7 +318,7 @@ amd_mcheck_init(const struct cpuinfo_x86
         mcequirk_amd_apply(quirkflag);
 
     if ( cpu_has(c, X86_FEATURE_AMD_PPIN) &&
-         (c == &boot_cpu_data || ppin_msr) )
+         (bsp || ppin_msr) )
     {
         uint64_t val;
 
@@ -333,7 +333,7 @@ amd_mcheck_init(const struct cpuinfo_x86
 
         if ( !(val & PPIN_ENABLE) )
             ppin_msr = 0;
-        else if ( c == &boot_cpu_data )
+        else if ( bsp )
             ppin_msr = MSR_AMD_PPIN;
     }
 
--- a/xen/arch/x86/cpu/mcheck/mce_intel.c
+++ b/xen/arch/x86/cpu/mcheck/mce_intel.c
@@ -85,7 +85,7 @@ static void cf_check intel_thermal_inter
 }
 
 /* Thermal monitoring depends on APIC, ACPI and clock modulation */
-static bool intel_thermal_supported(struct cpuinfo_x86 *c)
+static bool intel_thermal_supported(const struct cpuinfo_x86 *c)
 {
     if ( !cpu_has_apic )
         return false;
@@ -108,7 +108,7 @@ static void __init mcheck_intel_therm_in
 }
 
 /* P4/Xeon Thermal regulation detect and init */
-static void intel_init_thermal(struct cpuinfo_x86 *c)
+static void intel_init_thermal(const struct cpuinfo_x86 *c, bool bsp)
 {
     uint64_t msr_content;
     uint32_t val;
@@ -141,7 +141,7 @@ static void intel_init_thermal(struct cp
     if ( (msr_content & (1ULL<<3))
          && (val & APIC_DM_MASK) == APIC_DM_SMI )
     {
-        if ( c == &boot_cpu_data )
+        if ( bsp )
             printk(KERN_DEBUG "Thermal monitoring handled by SMI\n");
         return; /* -EBUSY */
     }
@@ -152,7 +152,7 @@ static void intel_init_thermal(struct cp
     /* check whether a vector already exists, temporarily masked? */
     if ( val & APIC_VECTOR_MASK )
     {
-        if ( c == &boot_cpu_data )
+        if ( bsp )
             printk(KERN_DEBUG "Thermal LVT vector (%#x) already installed\n",
                    val & APIC_VECTOR_MASK);
         return; /* -EBUSY */
@@ -850,7 +850,7 @@ static void intel_init_mce(bool bsp)
     mce_uhandler_num = ARRAY_SIZE(intel_mce_uhandlers);
 }
 
-static void intel_init_ppin(const struct cpuinfo_x86 *c)
+static void intel_init_ppin(const struct cpuinfo_x86 *c, bool bsp)
 {
     /*
      * Even if testing the presence of the MSR would be enough, we don't
@@ -878,7 +878,7 @@ static void intel_init_ppin(const struct
     case 0x6c: /* Icelake D */
     case 0x8f: /* Sapphire Rapids X */
 
-        if ( (c != &boot_cpu_data && !ppin_msr) ||
+        if ( (!bsp && !ppin_msr) ||
              rdmsr_safe(MSR_PPIN_CTL, val) )
             return;
 
@@ -891,7 +891,7 @@ static void intel_init_ppin(const struct
 
         if ( !(val & PPIN_ENABLE) )
             ppin_msr = 0;
-        else if ( c == &boot_cpu_data )
+        else if ( bsp )
             ppin_msr = MSR_PPIN;
 
         break;
@@ -992,9 +992,9 @@ enum mcheck_type intel_mcheck_init(struc
 
     intel_init_cmci(c);
 
-    intel_init_thermal(c);
+    intel_init_thermal(c, bsp);
 
-    intel_init_ppin(c);
+    intel_init_ppin(c, bsp);
 
     return mcheck_intel;
 }