Re: [PATCH 5/6] x86/paravirt: Switch MSR access pv_ops functions to instruction interfaces

["H. Peter Anvin" <hpa@xxxxxxxxx>]

On May 12, 2025 11:06:02 PM PDT, "Jürgen Groß" <jgross@xxxxxxxx> wrote:
>On 13.05.25 07:55, Xin Li wrote:
>> On 5/12/2025 4:24 AM, Juergen Gross wrote:
>>> Now with the mentioned patch really attached. :-)
>>> 
>> 
>> Does it allow patching with an instruction more than 6 bytes long?
>> 
>> The immediate form MSR instructions are 9 bytes long.
>
>Yes, shouldn't be a problem.
>
>
>Juergen

However, it is more than that. The immediate instructions have a different 
interface, and it makes more sense to use the extra bytes to shuffle the bits 
around for the legacy forms:

Write:

    mov %rax,%rdx
    shr $32,%rdx
    wrmsr(ns)

Read:

    rdmsr
    shl $32,%rdx
    or %rdx,%rax

For the write case, this also means that two separate trap points are needed.

As far as Xen (the only user of pv msrs), note that it only paravirtualizes a 
very small number of MSRs, and some of those are fairly performance sensitive, 
so not going through the Xen framework for MSRs known to be either native or 
null on Xen would definitely be a win.