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[PATCH v1 5/5] xen/arm: Enable workaround for Cortex-A53 erratum #1530924


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  • From: "Andrei Cherechesu (OSS)" <andrei.cherechesu@xxxxxxxxxxx>
  • Date: Tue, 10 Sep 2024 17:34:11 +0300
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  • Delivery-date: Tue, 10 Sep 2024 14:34:44 +0000
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From: Andrei Cherechesu <andrei.cherechesu@xxxxxxx>

All versions of Cortex-A53 cores are affected by the speculative
AT instruction erratum, as mentioned in the Cortex-A53 Revision r0
SDEN v21 documentation.

Enabled ARM64_WORKAROUND_AT_SPECULATE for all versions of Cortex-A53
cores, to avoid corrupting the TLB if performing a speculative AT
instruction during a guest context switch.

Signed-off-by: Andrei Cherechesu <andrei.cherechesu@xxxxxxx>
---
 docs/misc/arm/silicon-errata.txt | 1 +
 xen/arch/arm/cpuerrata.c         | 6 ++++++
 2 files changed, 7 insertions(+)

diff --git a/docs/misc/arm/silicon-errata.txt b/docs/misc/arm/silicon-errata.txt
index fffca09656..853e06aec1 100644
--- a/docs/misc/arm/silicon-errata.txt
+++ b/docs/misc/arm/silicon-errata.txt
@@ -46,6 +46,7 @@ stable hypervisors.
 | ARM            | Cortex-A53      | #824069         | ARM64_ERRATUM_824069    
|
 | ARM            | Cortex-A53      | #819472         | ARM64_ERRATUM_819472    
|
 | ARM            | Cortex-A53      | #843419         | ARM64_ERRATUM_843419    
|
+| ARM            | Cortex-A53      | #1530924        | N/A                     
|
 | ARM            | Cortex-A55      | #1530923        | N/A                     
|
 | ARM            | Cortex-A57      | #852523         | N/A                     
|
 | ARM            | Cortex-A57      | #832075         | ARM64_ERRATUM_832075    
|
diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c
index 2b7101ea25..afd0605922 100644
--- a/xen/arch/arm/cpuerrata.c
+++ b/xen/arch/arm/cpuerrata.c
@@ -683,6 +683,12 @@ static const struct arm_cpu_capabilities arm_errata[] = {
         .capability = ARM64_WORKAROUND_AT_SPECULATE,
         MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
     },
+    {
+        /* Cortex-A53 (All versions) */
+        .desc = "ARM erratum 1530924",
+        .capability = ARM64_WORKAROUND_AT_SPECULATE,
+        MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
+    },
     {},
 };
 
-- 
2.45.2




 


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