Re: [PATCH 4/6] x86/cpu-policy: MSR_ARCH_CAPS feature names

[Jan Beulich <jbeulich@xxxxxxxx>]

On 15.05.2023 16:42, Andrew Cooper wrote:
> Seed the default visibility from the dom0 special case, which for the most
> part just exposes the *_NO bits.

EIBRS and SKIP_L1DFL are outliers here, in not presently being exposed
to Dom0. If (latent) exposing of them wasn't an oversight, then this would
imo want justifying here. They'll get exposed, after all, ...

>  Insert a block dependency from the ARCH_CAPS
> CPUID bit to the entire content of the MSR.
> 
> The overall CPUID bit is still max-only, so all of MSR_ARCH_CAPS is hidden in
> the default policies.

... once this changes, as they're also not just 'a', but 'A'.

> --- a/tools/misc/xen-cpuid.c
> +++ b/tools/misc/xen-cpuid.c
> @@ -228,6 +228,19 @@ static const char *const str_7d2[32] =
>  
>  static const char *const str_10Al[32] =
>  {
> +    [ 0] = "rdcl-no",             [ 1] = "eibrs",
> +    [ 2] = "rsba",                [ 3] = "skip-l1dfl",
> +    [ 4] = "intel-ssb-no",        [ 5] = "mds-no",
> +    [ 6] = "if-pschange-mc-no",   [ 7] = "tsx-ctrl",
> +    [ 8] = "taa-no",              [ 9] = "mcu-ctrl",
> +    [10] = "misc-pkg-ctrl",       [11] = "energy-ctrl",

Not "energy-filtering" or "energy-filtering-ctl" for the right one here?

> +    [12] = "doitm",               [13] = "sbdr-ssdp-no",
> +    [14] = "fbsdp-no",            [15] = "psdp-no",
> +    /* 16 */                      [17] = "fb-clear",
> +    [18] = "fb-clear-ctrl",       [19] = "rrsba",
> +    [20] = "bhi-no",              [21] = "xapic-status",
> +    /* 22 */                      [23] = "ovrclk-status",
> +    [24] = "pbrsb-no",
>  };
>  
>  static const char *const str_10Ah[32] =
> --- a/xen/include/public/arch-x86/cpufeatureset.h
> +++ b/xen/include/public/arch-x86/cpufeatureset.h
> @@ -308,6 +308,29 @@ XEN_CPUFEATURE(AVX_NE_CONVERT,     15*32+ 5) /*A  
> AVX-NE-CONVERT Instructions */
>  XEN_CPUFEATURE(CET_SSS,            15*32+18) /*   CET Supervisor Shadow 
> Stacks safe to use */
>  
>  /* Intel-defined CPU features, MSR_ARCH_CAPS 0x10a.eax, word 16 */
> +XEN_CPUFEATURE(RDCL_NO,            16*32+ 0) /*A  No Rogue Data Cache Load 
> (Meltdown) */
> +XEN_CPUFEATURE(EIBRS,              16*32+ 1) /*A  Enhanced IBRS */
> +XEN_CPUFEATURE(RSBA,               16*32+ 2) /*!A RSB Alternative (Retpoline 
> not safe) */
> +XEN_CPUFEATURE(SKIP_L1DFL,         16*32+ 3) /*A  Don't need to flush L1D on 
> VMEntry */
> +XEN_CPUFEATURE(INTEL_SSB_NO,       16*32+ 4) /*A  No Speculative Store 
> Bypass */
> +XEN_CPUFEATURE(MDS_NO,             16*32+ 5) /*A  No Microarchitectural Data 
> Sampling */
> +XEN_CPUFEATURE(IF_PSCHANGE_MC_NO,  16*32+ 6) /*A  No Instruction fetch #MC */
> +XEN_CPUFEATURE(TSX_CTRL,           16*32+ 7) /*   MSR_TSX_CTRL */
> +XEN_CPUFEATURE(TAA_NO,             16*32+ 8) /*A  No TSX Async Abort */
> +XEN_CPUFEATURE(MCU_CTRL,           16*32+ 9) /*   MSR_MCU_CTRL */
> +XEN_CPUFEATURE(MISC_PKG_CTRL,      16*32+10) /*   MSR_MISC_PKG_CTRL */
> +XEN_CPUFEATURE(ENERGY_FILTERING,   16*32+11) /*   
> MSR_MISC_PKG_CTRL.ENERGY_FILTERING */

These last two aren't exactly in sync with the SDM; I assume that's
intended?

> +XEN_CPUFEATURE(DOITM,              16*32+12) /*   Data Operand Invariant 
> Timing Mode */
> +XEN_CPUFEATURE(SBDR_SSBD_NO,       16*32+13) /*A  No Shared Buffer Data Read 
> or Sideband Stale Data Propagation */

SBDR_SSDP_NO?

> +XEN_CPUFEATURE(FBDSP_NO,           16*32+14) /*A  No Fill Buffer Stale Data 
> Propagation */

FBSDP_NO?

Jan