[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v4 3/4] x86: limit issuing of IBPB during context switch
- To: "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- From: Jan Beulich <jbeulich@xxxxxxxx>
- Date: Tue, 14 Feb 2023 17:11:40 +0100
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=suse.com; dmarc=pass action=none header.from=suse.com; dkim=pass header.d=suse.com; arc=none
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=VsxokRwRk6IFeqdM2G8OVgIpJfgzhXYhcx1m6t7JxXU=; b=hRv+o2iB3ts4eeUUw7Eujg5jTu3qRqL/O2p7jQPPLlFul8LTiQKXFyuBaG+tQlHbjEP3AK/rPoVhAnMbPhI+NQOOUZEAKyhb9PRu7RcR61dcFf0y/fooWqqcvDO18ttuGHUPq50z33xgxqq5kurCm2/8hC7Lkly9MI+hxFVUCbFzVYj1UrWvAv06j/SbZ40tm7b9WkGQzocFm0KkncMZ5wKjQoVg+71b7hRi8QZBfa1T3TZf03g0aZP3NppXEuQltDqPNz4XgfyA2kn/DUhRsge6XibOAKrYABJ1fnbTrYguCWHe3FlesOISNmJKpvWPmzW3XdPZYyBtP+ow6KalRw==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=JT8SwaaxGaqOdIlo6G/KwBNB0XjHtaMZzaQ7Y8YSFx8+2OIGnW20U4hPu2lYEs2aNrQf+QsXu79BcYBDZiKs0wVJ5HtLRvk+uX6CNZcALA/OwXBRg07zybGO0r+dnrWhXaPvTeznw893ZrXyDTE5Lb2sam2qgQVnLXAPAl1THgtwLyBaG+ibjiYJAartW8tNSCf+h5R1TJ1unVdx0u5jLNIlwRtiBnX1D9jn8aqtEZsZRH3BuO+UREgP/TQJF4HwVpVeR4xfXWgVr5uqFSzTjvOueemsy610vhp3Pzwze6OQWz1XdKRzd3H1tvLbbMrxkF4DwZJt7tnpoieyRW1LwA==
- Authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=suse.com;
- Cc: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>, Roger Pau Monné <roger.pau@xxxxxxxxxx>
- Delivery-date: Tue, 14 Feb 2023 16:11:45 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
When the outgoing vCPU had IBPB issued and RSB overwritten upon entering
Xen, then there's no need for a 2nd barrier during context switch.
Note that SCF_entry_ibpb is always clear for the idle domain, so no
explicit idle domain check is needed to augment the feature check
(which is simply inapplicable to "idle").
Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
---
v4: Tighten the condition.
v3: Fold into series.
---
I think in principle we could limit the impact from finding the idle
domain as "prevd", by having __context_switch() tell us what kind
domain's vCPU was switched out (it could still be "idle", but in fewer
cases).
--- a/xen/arch/x86/domain.c
+++ b/xen/arch/x86/domain.c
@@ -2005,17 +2005,26 @@ void context_switch(struct vcpu *prev, s
}
else
{
+ unsigned int feat_sc_rsb = X86_FEATURE_SC_RSB_HVM;
+
__context_switch();
/* Re-enable interrupts before restoring state which may fault. */
local_irq_enable();
if ( is_pv_domain(nextd) )
+ {
load_segments(next);
+ feat_sc_rsb = X86_FEATURE_SC_RSB_PV;
+ }
+
ctxt_switch_levelling(next);
- if ( opt_ibpb_ctxt_switch && !is_idle_domain(nextd) )
+ if ( opt_ibpb_ctxt_switch && !is_idle_domain(nextd) &&
+ (!(prevd->arch.spec_ctrl_flags & SCF_entry_ibpb) ||
+ /* is_idle_domain(prevd) || */
+ !boot_cpu_has(feat_sc_rsb)) )
{
static DEFINE_PER_CPU(unsigned int, last);
unsigned int *last_id = &this_cpu(last);
|