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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [PATCH v3 12/14] xen/riscv: introduce an implementation of macros from <asm/bug.h>
Hi, On 08/02/2023 12:00, Oleksii wrote: On Tue, 2023-02-07 at 16:07 +0100, Jan Beulich wrote:On 07.02.2023 15:46, Oleksii Kurochko wrote:--- /dev/null +++ b/xen/arch/riscv/include/asm/bug.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2012 Regents of the University of California + * Copyright (C) 2021-2023 Vates + * + */ +#ifndef _ASM_RISCV_BUG_H +#define _ASM_RISCV_BUG_H + +#include <xen/types.h> + +#ifndef __ASSEMBLY__ + +#define BUG_FN_REG t0 + +#define BUG_INSTR "ebreak" + +#define INSN_LENGTH_MASK _UL(0x3) +#define INSN_LENGTH_32 _UL(0x3)I assume these are deliberately over-simplified (not accounting for wider than 32-bit insns in any way)?The base instruction set has a fixed length of 32-bit naturally aligned instructions. There are extensions of variable length ( where each instruction can be any number of 16-bit parcels in length ) but they aren't used in Xen and Linux kernel ( where these definitions were taken from ). Compressed ISA is used now where the instruction length is 16 bit and 'ebreak' instruction, in this case, can be either 16 or 32 bit ( depending on if compressed ISA is used or not ) In other part of the code, you are using vaddr_t/paddr_t to describe an address. It would be best to use one of those (I think vaddr_t) so it is clear what kind of address it is supposed to take. Cheers, -- Julien Grall
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