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Need guidance to support reading GICR_TYPER (64 bit register) on Aarch32_v8r
- To: Julien Grall <julien@xxxxxxx>, "Stabellini, Stefano" <stefano.stabellini@xxxxxxx>, bertrand Marquis <Bertrand.Marquis@xxxxxxx>, "Volodymyr_Babchuk@xxxxxxxx" <Volodymyr_Babchuk@xxxxxxxx>, Henry Wang <Henry.Wang@xxxxxxx>, Penny Zheng <Penny.Zheng@xxxxxxx>
- From: Ayan Kumar Halder <ayankuma@xxxxxxx>
- Date: Thu, 13 Oct 2022 12:47:39 +0100
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- Cc: Jaxson Han <jaxson.han@xxxxxxx>, "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- Delivery-date: Thu, 13 Oct 2022 11:48:04 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
Hi Arm mantainers/Folks,
Please refer to the discussion
https://github.com/zephyrproject-rtos/zephyr/pull/51163 .
We intend to run Zephyr as a domU guest on Xen on Aarch32_v8R fixed
virtual platform.
Zephyr is trying to read GICR_TYPER which is a 64 bit register using
ldrd instruction.
As GICR is emulated by Xen, so this instruction gets trapped with HSR =
0x9200000c.
As ISV is 0, so Xen cannot emulate this instruction.
The proposed solution is to use two sys_read32() on GICR_TYPER to return
the lower and upper 32 bits.
With this, HSR = 0x9383 000c, ISV=1 so ISS is valid.
Now, for Xen to emulate this read, I have proposed the modifications (in
my last comment).
1. Does the proposed modifications look sane ? Or could there be a
better alternative ?
2. As there is no 32 bit variant for GICR_TYPER, so does it make sense
to read this register at all ?
Kind regards,
Ayan
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