RE: [PATCH v6 3/3] amd/msr: implement VIRT_SPEC_CTRL for HVM guests using legacy SSBD

[Henry Wang <Henry.Wang@xxxxxxx>]

Hi,

It seems that this series [1] has been stale for more than a month and also
this series seems to be properly reviewed and acked already. 

From what Jan has replied to Roger and Andrew:
"... this addition the series would now look to be ready to go in,
I'd like to have some form of confirmation by you, Andrew, that
you now view this as meeting the comments you gave on an earlier
version."

So I guess this can be merged. Sending this as a gentle reminder for
possible actions from Roger and Andrew. Thanks!

Also, not sure why my acked-by for the CHANGELOG.md is missing in
patchwork, just in case - for the change in CHANGELOG.md in patch#3:

Acked-by: Henry Wang <Henry.Wang@xxxxxxx>

[1] https://patchwork.kernel.org/project/xen-devel/list/?series=642413

Kind regards,
Henry

> -----Original Message-----
> From: Roger Pau Monne <roger.pau@xxxxxxxxxx>
> Subject: [PATCH v6 3/3] amd/msr: implement VIRT_SPEC_CTRL for HVM
> guests using legacy SSBD
> 
> Expose VIRT_SSBD to guests if the hardware supports setting SSBD in
> the LS_CFG MSR (a.k.a. non-architectural way). Different AMD CPU
> families use different bits in LS_CFG, so exposing VIRT_SPEC_CTRL.SSBD
> allows for an unified way of exposing SSBD support to guests on AMD
> hardware that's compatible migration wise, regardless of what
> underlying mechanism is used to set SSBD.
> 
> Note that on AMD Family 17h and Hygon Family 18h processors the value
> of SSBD in LS_CFG is shared between threads on the same core, so
> there's extra logic in order to synchronize the value and have SSBD
> set as long as one of the threads in the core requires it to be set.
> Such logic also requires extra storage for each thread state, which is
> allocated at initialization time.
> 
> Do the context switching of the SSBD selection in LS_CFG between
> hypervisor and guest in the same handler that's already used to switch
> the value of VIRT_SPEC_CTRL.
> 
> Suggested-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
> Signed-off-by: Roger Pau Monné <roger.pau@xxxxxxxxxx>
> Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>
> ---
> Changes since v5:
>  - Fix one codding style issue.
> 
> Changes since v4:
>  - Slightly change usage of val/opt_ssbd in
>    vm{exit,entry}_virt_spec_ctrl.
>  - Pull opt_ssbd outside of the for loop in amd_setup_legacy_ssbd().
>  - Fix indentation.
>  - Remove ASSERTs/BUG_ONs from GIF=0 context.
> 
> Changes since v3:
>  - Align ssbd per-core struct to a cache line.
>  - Open code a simple spinlock to avoid playing tricks with the lock
>    detector.
>  - s/ssbd_core/ssbd_ls_cfg/.
>  - Fix log message wording.
>  - Fix define name and remove comment.
>  - Also handle Hygon processors (Fam18h).
>  - Add changelog entry.
> 
> Changes since v2:
>  - Fix codding style issues.
>  - Use AMD_ZEN1_MAX_SOCKETS to define the max number of possible
>    sockets in Zen1 systems.
> 
> Changes since v1:
>  - Report legacy SSBD support using a global variable.
>  - Use ro_after_init for ssbd_max_cores.
>  - Handle boot_cpu_data.x86_num_siblings < 1.
>  - Add comment regarding _irqsave usage in amd_set_legacy_ssbd.
> ---
>  CHANGELOG.md                   |   3 +
>  xen/arch/x86/cpu/amd.c         | 121 ++++++++++++++++++++++++++++-----
>  xen/arch/x86/hvm/svm/svm.c     |   4 ++
>  xen/arch/x86/include/asm/amd.h |   4 ++
>  xen/arch/x86/spec_ctrl.c       |   4 +-
>  5 files changed, 118 insertions(+), 18 deletions(-)
> 
> diff --git a/CHANGELOG.md b/CHANGELOG.md
> index 6a7755d7b0..9a007e2513 100644
> --- a/CHANGELOG.md
> +++ b/CHANGELOG.md
> @@ -13,6 +13,9 @@ The format is based on [Keep a
> Changelog](https://keepachangelog.com/en/1.0.0/)
>  ### Removed / support downgraded
>   - dropped support for the (x86-only) "vesa-mtrr" and "vesa-remap"
> command line options
> 
> +### Added
> + - Support VIRT_SSBD feature for HVM guests on AMD.
> +
>  ## [4.16.0](https://xenbits.xen.org/gitweb/?p=xen.git;a=shortlog;h=staging)
> - 2021-12-02
> 
>  ### Removed
> diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
> index 4999f8be2b..5f9e734e84 100644
> --- a/xen/arch/x86/cpu/amd.c
> +++ b/xen/arch/x86/cpu/amd.c
> @@ -48,6 +48,7 @@ boolean_param("allow_unsafe", opt_allow_unsafe);
> 
>  /* Signal whether the ACPI C1E quirk is required. */
>  bool __read_mostly amd_acpi_c1e_quirk;
> +bool __ro_after_init amd_legacy_ssbd;
> 
>  static inline int rdmsr_amd_safe(unsigned int msr, unsigned int *lo,
>                                unsigned int *hi)
> @@ -685,23 +686,10 @@ void amd_init_lfence(struct cpuinfo_x86 *c)
>   * Refer to the AMD Speculative Store Bypass whitepaper:
>   * https://developer.amd.com/wp-
> content/resources/124441_AMD64_SpeculativeStoreBypassDisable_White
> paper_final.pdf
>   */
> -void amd_init_ssbd(const struct cpuinfo_x86 *c)
> +static bool set_legacy_ssbd(const struct cpuinfo_x86 *c, bool enable)
>  {
>       int bit = -1;
> 
> -     if (cpu_has_ssb_no)
> -             return;
> -
> -     if (cpu_has_amd_ssbd) {
> -             /* Handled by common MSR_SPEC_CTRL logic */
> -             return;
> -     }
> -
> -     if (cpu_has_virt_ssbd) {
> -             wrmsrl(MSR_VIRT_SPEC_CTRL, opt_ssbd ?
> SPEC_CTRL_SSBD : 0);
> -             return;
> -     }
> -
>       switch (c->x86) {
>       case 0x15: bit = 54; break;
>       case 0x16: bit = 33; break;
> @@ -715,20 +703,119 @@ void amd_init_ssbd(const struct cpuinfo_x86 *c)
>               if (rdmsr_safe(MSR_AMD64_LS_CFG, val) ||
>                   ({
>                           val &= ~mask;
> -                         if (opt_ssbd)
> +                         if (enable)
>                                   val |= mask;
>                           false;
>                   }) ||
>                   wrmsr_safe(MSR_AMD64_LS_CFG, val) ||
>                   ({
>                           rdmsrl(MSR_AMD64_LS_CFG, val);
> -                         (val & mask) != (opt_ssbd * mask);
> +                         (val & mask) != (enable * mask);
>                   }))
>                       bit = -1;
>       }
> 
> -     if (bit < 0)
> +     return bit >= 0;
> +}
> +
> +void amd_init_ssbd(const struct cpuinfo_x86 *c)
> +{
> +     if (cpu_has_ssb_no)
> +             return;
> +
> +     if (cpu_has_amd_ssbd) {
> +             /* Handled by common MSR_SPEC_CTRL logic */
> +             return;
> +     }
> +
> +     if (cpu_has_virt_ssbd) {
> +             wrmsrl(MSR_VIRT_SPEC_CTRL, opt_ssbd ?
> SPEC_CTRL_SSBD : 0);
> +             return;
> +     }
> +
> +     if (!set_legacy_ssbd(c, opt_ssbd)) {
>               printk_once(XENLOG_ERR "No SSBD controls available\n");
> +             if (amd_legacy_ssbd)
> +                     panic("CPU feature mismatch: no legacy SSBD\n");
> +     } else if (c == &boot_cpu_data)
> +             amd_legacy_ssbd = true;
> +}
> +
> +static struct ssbd_ls_cfg {
> +    bool locked;
> +    unsigned int count;
> +} __cacheline_aligned *ssbd_ls_cfg;
> +static unsigned int __ro_after_init ssbd_max_cores;
> +#define AMD_FAM17H_MAX_SOCKETS 2
> +
> +bool __init amd_setup_legacy_ssbd(void)
> +{
> +     unsigned int i;
> +
> +     if ((boot_cpu_data.x86 != 0x17 && boot_cpu_data.x86 != 0x18) ||
> +         boot_cpu_data.x86_num_siblings <= 1)
> +             return true;
> +
> +     /*
> +      * One could be forgiven for thinking that c->x86_max_cores is the
> +      * correct value to use here.
> +      *
> +      * However, that value is derived from the current configuration,
> and
> +      * c->cpu_core_id is sparse on all but the top end CPUs.  Derive
> +      * max_cpus from ApicIdCoreIdSize which will cover any sparseness.
> +      */
> +     if (boot_cpu_data.extended_cpuid_level >= 0x80000008) {
> +             ssbd_max_cores = 1u <<
> MASK_EXTR(cpuid_ecx(0x80000008), 0xf000);
> +             ssbd_max_cores /= boot_cpu_data.x86_num_siblings;
> +     }
> +     if (!ssbd_max_cores)
> +             return false;
> +
> +     ssbd_ls_cfg = xzalloc_array(struct ssbd_ls_cfg,
> +                                 ssbd_max_cores * AMD_FAM17H_MAX_SOCKETS);
> +     if (!ssbd_ls_cfg)
> +             return false;
> +
> +     if (opt_ssbd)
> +             for (i = 0; i < ssbd_max_cores *
> AMD_FAM17H_MAX_SOCKETS; i++)
> +                     /* Set initial state, applies to any (hotplug) CPU. */
> +                     ssbd_ls_cfg[i].count =
> boot_cpu_data.x86_num_siblings;
> +
> +     return true;
> +}
> +
> +/*
> + * Executed from GIF==0 context: avoid using BUG/ASSERT or other
> functionality
> + * that relies on exceptions as those are not expected to run in GIF==0
> + * context.
> + */
> +void amd_set_legacy_ssbd(bool enable)
> +{
> +     const struct cpuinfo_x86 *c = &current_cpu_data;
> +     struct ssbd_ls_cfg *status;
> +
> +     if ((c->x86 != 0x17 && c->x86 != 0x18) || c->x86_num_siblings <= 1)
> {
> +             set_legacy_ssbd(c, enable);
> +             return;
> +     }
> +
> +     status = &ssbd_ls_cfg[c->phys_proc_id * ssbd_max_cores +
> +                           c->cpu_core_id];
> +
> +     /*
> +      * Open code a very simple spinlock: this function is used with
> GIF==0
> +      * and different IF values, so would trigger the checklock detector.
> +      * Instead of trying to workaround the detector, use a very simple
> lock
> +      * implementation: it's better to reduce the amount of code
> executed
> +      * with GIF==0.
> +      */
> +     while (test_and_set_bool(status->locked))
> +             cpu_relax();
> +     status->count += enable ? 1 : -1;
> +     if (enable ? status->count == 1 : !status->count)
> +             set_legacy_ssbd(c, enable);
> +     barrier();
> +     write_atomic(&status->locked, false);
>  }
> 
>  void __init detect_zen2_null_seg_behaviour(void)
> diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c
> index c4bdeaff52..3cc5fcdc44 100644
> --- a/xen/arch/x86/hvm/svm/svm.c
> +++ b/xen/arch/x86/hvm/svm/svm.c
> @@ -3126,6 +3126,8 @@ void vmexit_virt_spec_ctrl(void)
> 
>      if ( cpu_has_virt_ssbd )
>          wrmsr(MSR_VIRT_SPEC_CTRL, val, 0);
> +    else
> +        amd_set_legacy_ssbd(val);
>  }
> 
>  /* Called with GIF=0. */
> @@ -3138,6 +3140,8 @@ void vmentry_virt_spec_ctrl(void)
> 
>      if ( cpu_has_virt_ssbd )
>          wrmsr(MSR_VIRT_SPEC_CTRL, val, 0);
> +    else
> +        amd_set_legacy_ssbd(val);
>  }
> 
>  /*
> diff --git a/xen/arch/x86/include/asm/amd.h
> b/xen/arch/x86/include/asm/amd.h
> index a82382e6bf..6a42f68542 100644
> --- a/xen/arch/x86/include/asm/amd.h
> +++ b/xen/arch/x86/include/asm/amd.h
> @@ -151,4 +151,8 @@ void check_enable_amd_mmconf_dmi(void);
>  extern bool amd_acpi_c1e_quirk;
>  void amd_check_disable_c1e(unsigned int port, u8 value);
> 
> +extern bool amd_legacy_ssbd;
> +bool amd_setup_legacy_ssbd(void);
> +void amd_set_legacy_ssbd(bool enable);
> +
>  #endif /* __AMD_H__ */
> diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c
> index 0d5ec877d1..495e6f9405 100644
> --- a/xen/arch/x86/spec_ctrl.c
> +++ b/xen/arch/x86/spec_ctrl.c
> @@ -22,6 +22,7 @@
>  #include <xen/param.h>
>  #include <xen/warning.h>
> 
> +#include <asm/amd.h>
>  #include <asm/hvm/svm/svm.h>
>  #include <asm/microcode.h>
>  #include <asm/msr.h>
> @@ -1073,7 +1074,8 @@ void __init init_speculation_mitigations(void)
>      }
> 
>      /* Support VIRT_SPEC_CTRL.SSBD if AMD_SSBD is not available. */
> -    if ( opt_msr_sc_hvm && !cpu_has_amd_ssbd && cpu_has_virt_ssbd )
> +    if ( opt_msr_sc_hvm && !cpu_has_amd_ssbd &&
> +         (cpu_has_virt_ssbd || (amd_legacy_ssbd &&
> amd_setup_legacy_ssbd())) )
>          setup_force_cpu_cap(X86_FEATURE_VIRT_SC_MSR_HVM);
> 
>      /* If we have IBRS available, see whether we should use it. */
> --
> 2.36.0