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Re: [PATCH v1 03/10] xue: add support for selecting specific xhci


  • To: Marek Marczykowski-Górecki <marmarek@xxxxxxxxxxxxxxxxxxxxxx>
  • From: Jan Beulich <jbeulich@xxxxxxxx>
  • Date: Wed, 15 Jun 2022 16:40:35 +0200
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  • Cc: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, George Dunlap <george.dunlap@xxxxxxxxxx>, Julien Grall <julien@xxxxxxx>, Stefano Stabellini <sstabellini@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>, xen-devel@xxxxxxxxxxxxxxxxxxxx
  • Delivery-date: Wed, 15 Jun 2022 14:40:44 +0000
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>

On 07.06.2022 16:30, Marek Marczykowski-Górecki wrote:
> --- a/docs/misc/xen-command-line.pandoc
> +++ b/docs/misc/xen-command-line.pandoc
> @@ -721,10 +721,15 @@ Available alternatives, with their meaning, are:
>  
>  ### dbgp
>  > `= ehci[ <integer> | @pci<bus>:<slot>.<func> ]`
> +> `= xue[ <integer> | @pci<bus>:<slot>.<func> ]`
>  
>  Specify the USB controller to use, either by instance number (when going
>  over the PCI busses sequentially) or by PCI device (must be on segment 0).
>  
> +Use `ehci` for EHCI debug port, use `xue` for XHCI debug capability.

Ah, this answers one of my questions on patch 1. But I still think
the option should appear here in patch 1, with this patch extending
it (and its doc).

> --- a/xen/drivers/char/xue.c
> +++ b/xen/drivers/char/xue.c
> @@ -204,6 +204,7 @@ struct xue {
>      void *xhc_mmio;
>  
>      int open;
> +    int xhc_num; /* look for n-th xhc */

unsigned int?

> @@ -252,24 +253,34 @@ static int xue_init_xhc(struct xue *xue)
>      uint64_t bar1;
>      uint64_t devfn;
>  
> -    /*
> -     * Search PCI bus 0 for the xHC. All the host controllers supported so 
> far
> -     * are part of the chipset and are on bus 0.
> -     */
> -    for ( devfn = 0; devfn < 256; devfn++ ) {
> -        uint32_t dev = (devfn & 0xF8) >> 3;
> -        uint32_t fun = devfn & 0x07;
> -        pci_sbdf_t sbdf = PCI_SBDF(0, dev, fun);
> -        uint32_t hdr = pci_conf_read8(sbdf, PCI_HEADER_TYPE);
> -
> -        if ( hdr == 0 || hdr == 0x80 )
> +    if ( xue->sbdf.sbdf == 0 )
> +    {
> +        /*
> +         * Search PCI bus 0 for the xHC. All the host controllers supported 
> so far
> +         * are part of the chipset and are on bus 0.
> +         */
> +        for ( devfn = 0; devfn < 256; devfn++ )
>          {
> -            if ( (pci_conf_read32(sbdf, PCI_CLASS_REVISION) >> 8) == 
> XUE_XHC_CLASSC )
> +            uint32_t dev = (devfn & 0xF8) >> 3;
> +            uint32_t fun = devfn & 0x07;
> +            pci_sbdf_t sbdf = PCI_SBDF(0, dev, fun);
> +            uint32_t hdr = pci_conf_read8(sbdf, PCI_HEADER_TYPE);
> +
> +            if ( hdr == 0 || hdr == 0x80 )
>              {
> -                xue->sbdf = sbdf;
> -                break;
> +                if ( (pci_conf_read32(sbdf, PCI_CLASS_REVISION) >> 8) == 
> XUE_XHC_CLASSC )
> +                {
> +                    if ( xue->xhc_num-- )
> +                        continue;
> +                    xue->sbdf = sbdf;
> +                    break;
> +                }
>              }
>          }
> +    } else {

Nit:

    }
    else
    {

Jan



 


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