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Re: [PATCH 3/5] x86/perf: expose LBR format in PERF_CAPABILITIES
- To: Andrew Cooper <Andrew.Cooper3@xxxxxxxxxx>
- From: Jan Beulich <jbeulich@xxxxxxxx>
- Date: Fri, 20 May 2022 16:19:19 +0200
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- Cc: Wei Liu <wl@xxxxxxx>, Roger Pau Monne <roger.pau@xxxxxxxxxx>, "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- Delivery-date: Fri, 20 May 2022 14:19:34 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 20.05.2022 16:10, Andrew Cooper wrote:
> On 20/05/2022 14:37, Roger Pau Monne wrote:
>> --- a/xen/include/public/arch-x86/cpufeatureset.h
>> +++ b/xen/include/public/arch-x86/cpufeatureset.h
>> @@ -135,7 +135,7 @@ XEN_CPUFEATURE(SSSE3, 1*32+ 9) /*A Supplemental
>> Streaming SIMD Extensio
>> XEN_CPUFEATURE(FMA, 1*32+12) /*A Fused Multiply Add */
>> XEN_CPUFEATURE(CX16, 1*32+13) /*A CMPXCHG16B */
>> XEN_CPUFEATURE(XTPR, 1*32+14) /* Send Task Priority Messages */
>> -XEN_CPUFEATURE(PDCM, 1*32+15) /* Perf/Debug Capability MSR */
>> +XEN_CPUFEATURE(PDCM, 1*32+15) /*S Perf/Debug Capability MSR */
>
> This is the bit which requires more toolstack logic to safely enable.
> Using 's' for off-by-default is fine if we want to get the series in now.
>
> But before we expose the MSR generally, we need to:
>
> 1) Put the configuration in msr_policy so the toolstack can reason about it
> 2) Reject migration attempts to destinations where the LBR format changes
Since this could be quite restrictive, and since people needing to know
they need to hide this feature for migration to work, I guess this would
further want qualifying by "did the guest actually use LBRs so far"?
Jan
> 3) Actually put the lBR registers in the migration stream
>
> ~Andrew
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