[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH] x86/msr: handle reads to MSR_P5_MC_ADDR


  • To: Roger Pau Monne <roger.pau@xxxxxxxxxx>
  • From: Jan Beulich <jbeulich@xxxxxxxx>
  • Date: Thu, 28 Apr 2022 09:55:33 +0200
  • Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=suse.com; dmarc=pass action=none header.from=suse.com; dkim=pass header.d=suse.com; arc=none
  • Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=UH3WRMXNzMgz6xBZXjnATnCw0a/JPuWXgxwv0LToAC0=; b=iJ3EFg1zQaIrfsX0L6GsXL/44KZCRaIXpZcIMDBkOXvgXXAW741nEEhgKOdSz8NuPMQ80k3sEzpLe6mC0MCxEjDoN6Y/qZjHeJgE9KR8KyhNB9QFTpIKBbjlt/QyTX0kkVKe1XSCjhwqWk0yoGC+zwGveehNFUBdbAVG2TYPKiL8m7s7pZBsp/buNQCjnZB09t4dct/DU059nRZJrTAneX+bnxCLMLtyUyZv8wU3h4l5TbKwZsjHNDIr2TScHq/lWi94MqhvSo6SojjMkaOlPLAoobX5JR+IqMI4ZB60gcDlG/dJH00mK30fOBnrwzppxMkB/fYJtBSwPTfhwX9lVw==
  • Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=KdGsRI4Dds1FoCQ7Y66yQ+U0jNjMFRn9hFOLHjLTAWia2vxQWKQevSvzrWoEJKKoZuVPMfhWZuYj2Ak0ghYZcBAsCnRRPI0Pzb5rdbtR6n0cLzgBr4f5wIufH65vH7NNOSQhFP/PrBA/35jL3tL09AwZ/xQRga2Fo3dnTmq1Zcu0pjSLc5OHbZ99WC973vYeatI1VujvO7ShxjoNN8JtgizpsMRc+5MmZVWIH4TvkajmY+lbkOv6ZeuYob9e3eHPlCriykhz1y9vFY+XSXxi76VFlgJXvlat60eLeegoVSsM6CeZk/kr9v6fH5WFepfRi3V4IOlU1oZv5LF4i5bfbQ==
  • Authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=suse.com;
  • Cc: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>, Steffen Einsle <einsle@xxxxxxxxxx>, xen-devel@xxxxxxxxxxxxxxxxxxxx
  • Delivery-date: Thu, 28 Apr 2022 07:55:42 +0000
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>

On 27.04.2022 17:47, Roger Pau Monne wrote:
> I've added it for CENTAUR and SHANGHAI because the MSR is there since
> Pentium, so likely to be implemented by those vendors also, but have
> no way to check.

I think that's fine.

> I wonder how long it will take for Windows to also start poking at
> MSR_IA32_MC0_ADDR or other MCE related registers.  For now this seems
> to be enough.

Those are handled by vmce_{rd,wr}msr(), aren't they? As a result I
wonder whether the MSR in question as well as its companion
P5_MC_TYPE wouldn't better also be handled (faked) there. (Even if
not, I don't think we should handle ADDR by not TYPE.)

Jan




 


Rackspace

Lists.xenproject.org is hosted with RackSpace, monitoring our
servers 24x7x365 and backed by RackSpace's Fanatical Support®.