[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v3 0/3] amd/msr: implement MSR_VIRT_SPEC_CTRL for HVM guests
- To: <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- From: Roger Pau Monne <roger.pau@xxxxxxxxxx>
- Date: Thu, 31 Mar 2022 11:27:14 +0200
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=citrix.com; dmarc=pass action=none header.from=citrix.com; dkim=pass header.d=citrix.com; arc=none
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=2mS2ShJkHIoRZHGPPQN0koP60ywG8SarWw/5svPvWms=; b=RftWA/xbCifd+DUsWYlituUlJ4qTF6VXSOKVlEZnRLqS7nxmLHt0c0eCGEgGMeQmTude9U+mCgodky97gw+6GAcPfVYu7A6EfeD9GiehJA2jUzLWjODorLrGroVoYHrp604qQhqRJNr+04MoJd9UxMN9a4QN3CYIbrcQouznoExX45APgHcetrIvdtTLl6oCIKnTtUaCg+EoCkpWBVe+Aq6W6vq0tv3KWYXNpDdU9MVEUttn3RtkhQlrRxY8qzbm7FpCgHb/mLSK4noED3VFvfaT6rz1k79mBZ7g8Rr46UGaQhwLKlWrkjkeQPhKZCcY00fjwluLS7grKQ4yU9l9Hg==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=X3Qr0r4aPWbzUuyOOLXDelQj5+l/Elky3KnQY6W/mJ0yytTX4ewajFiAn7hyQCPtKTVQSsTBf7U5gxuUj154TpF0Ws7gNKyTTIzx92i/bL/qlweQLeaFZSq2BvEY9Wq7jeMdtuGFygAh9g79mXnK8o4tlefU6HbRSUvCcW5nKRcF8ZMlP0Izfo0XZ+Xcl916Rjgx9W2HqBYx1O9ni5yRBKrGKqWrrtisgYJh4HX01GrMDiHHOTEkfckCvxQVXs2olxcMExVPcZL/CPS6DchskCQvV6MLtuX+hSySla3+XmSrLbfGlT8j7ZUeDLp10FKzorO7XusqjmEePdyTpQFFgA==
- Authentication-results: esa3.hc3370-68.iphmx.com; dkim=pass (signature verified) header.i=@citrix.onmicrosoft.com
- Cc: Roger Pau Monne <roger.pau@xxxxxxxxxx>, Jan Beulich <jbeulich@xxxxxxxx>, Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>
- Delivery-date: Thu, 31 Mar 2022 09:29:00 +0000
- Ironport-data: A9a23:EUpPN6nfda7ECmF27l1q92Po5gyWJkRdPkR7XQ2eYbSJt1+Wr1Gzt xIZCDvVb/qLajejfN8nYdzi9BkO7JfQy9VhG1BtqXg1QyMWpZLJC+rCIxarNUt+DCFioGGLT Sk6QoOdRCzhZiaE/n9BCpC48T8kk/vgqoPUUIYoAAgoLeNfYHpn2EoLd9IR2NYy24DiWFrV4 LsenuWEULOb828sWo4rw/rrRCNH5JwebxtB4zTSzdgS1LPvvyF94KA3fMldHFOhKmVgJcaoR v6r8V2M1jixEyHBqD+Suu2TnkUiGtY+NOUV45Zcc/DKbhNq/kTe3kunXRa1hIg+ZzihxrhMJ NtxWZOYSFcMEJeLtc4nVkcBPCE5JPReypzpPi3q2SCT5xWun3rExvxvCAc9PJEC+/YxCmZLn RAaAGlTNFbZ3bvwme/lDLk37iggBJCD0Ic3oHZvwCufFf87aZvCX7/L9ZlT2zJYasVmQ6mAP JFJMmMHgBLofQFBZlpMK9EEvOqHvWf0LGRfsGq8nP9ii4TU5FMoi+W8WDbPQfSVQe1Fk0Deo XjJl0z7CBwHMN2UyRKe72mhwOTImEvTSI8UUbG16PNuqFmS3XAITg0bU0Ohpvu0gVL4XMhQQ 3H44QJ38/J0rhbyCICgAVvo+xZooyLwRfJRQ8gU0kag4JDRvV+2Bi8dFyZzS/I54ZpeqSMR6 neFmNbgBDpKubKTSG6A+rr8kQ5eKRT5PkdZO3ZaEFJtD83L5dhq00mRFooL/Lud1IWdJN3m/ 9ydQMHSbZ03hNVD6ai09Euvb9mE9smQFV5dCuk6swuYAuJFiGyNOtTABbvzt68owGOlor+p5 iJsdy+2trxmMH11vHbRKNjh5Znwjxp/DBXSgER0A74q/Cm39niocOh4uW8idBk3b5laI2K2P Sc/XD+9ArcJZhNGioctPuqM5zkCl/C8RbwJqNiKBjaxXnSBXFDep3w/DaJh92vsjFItgckC1 WSzKq6R4YIhIf0/llKeHr5FuZdyn3xW7T6DFPjTkkX8uZLDNSH9dFvwGAbXBgzPxPjf+1u9H hc2H5bi9iizp8WlPHGNqNRDfA1SRZX5bLivw/Fqmie4ClMOMEkqCuPLwKNnfIpgnq9PkfzP8 G37UUhdoGcTT1WeQelWQhiPsI/SYKs=
- Ironport-hdrordr: A9a23:QD5C+aM3QEWho8BcTsWjsMiBIKoaSvp037BN7TEXdfU1SL39qy nKpp8mPHDP5Ar5NEtOpTniAsm9qBHnm6KdiLN5Vd3OYOCMggqVBbAnwYz+wyDxXw3Sn9QtsJ uIqpIOa+EY22IK7/rH3A==
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
Hello,
The following series implements support for MSR_VIRT_SPEC_CTRL
(VIRT_SSBD) on different AMD CPU families.
Note that the support is added backwards, starting with the newer CPUs
that support MSR_SPEC_CTRL and moving to the older ones either using
MSR_VIRT_SPEC_CTRL or the SSBD bit in LS_CFG.
Xen is still free to use it's own SSBD setting, as the selection is
context switched on vm{entry,exit}.
On Zen2 and later, SPEC_CTRL.SSBD exists and should be used in
preference to VIRT_SPEC_CTRL.SSBD. However, for migration
compatibility, Xen offers VIRT_SSBD to guests (in the max CPUID policy,
not default) implemented in terms of SPEC_CTRL.SSBD.
On Fam15h thru Zen1, Xen exposes VIRT_SSBD to guests by default to
abstract away the model and/or hypervisor specific differences in
MSR_LS_CFG/MSR_VIRT_SPEC_CTRL.
Note that if the hardware itself does offer VIRT_SSBD (ie: very likely
when running virtualized on < Zen2 hardware) and not AMD_SSBD Xen will
allow untrapped access to MSR_VIRT_SPEC_CTRL for HVM guests.
So the implementation of VIRT_SSBD exposed to HVM guests will use one of
the following underlying mechanisms, in the preference order listed
below:
* SPEC_CTRL.SSBD. (patch 1)
* VIRT_SPEC_CTRL.SSBD (untrapped). (patch 2).
* Non-architectural way using LS_CFG. (patch 3)
This has survived a XenRT basic set of tests on AMD machines.
Roger Pau Monne (3):
amd/msr: implement VIRT_SPEC_CTRL for HVM guests on top of SPEC_CTRL
amd/msr: allow passthrough of VIRT_SPEC_CTRL for HVM guests
amd/msr: implement VIRT_SPEC_CTRL for HVM guests using legacy SSBD
xen/arch/x86/cpu/amd.c | 116 +++++++++++++++++---
xen/arch/x86/cpuid.c | 28 +++++
xen/arch/x86/hvm/hvm.c | 1 +
xen/arch/x86/hvm/svm/entry.S | 6 +
xen/arch/x86/hvm/svm/svm.c | 50 +++++++++
xen/arch/x86/include/asm/amd.h | 4 +
xen/arch/x86/include/asm/cpufeatures.h | 1 +
xen/arch/x86/include/asm/msr.h | 14 +++
xen/arch/x86/msr.c | 26 +++++
xen/arch/x86/spec_ctrl.c | 12 +-
xen/include/public/arch-x86/cpufeatureset.h | 2 +-
11 files changed, 241 insertions(+), 19 deletions(-)
--
2.35.1
|
