[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH v2 1/5] x86/cpuid: add CPUID flag for Extended Destination ID support


  • To: David Woodhouse <dwmw2@xxxxxxxxxxxxx>
  • From: Jan Beulich <jbeulich@xxxxxxxx>
  • Date: Thu, 17 Feb 2022 09:52:51 +0100
  • Arc-authentication-results: i=1; mx.microsoft.com 1; spf=none; dmarc=none; dkim=none; arc=none
  • Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=AIWwaZsNXUhbiUx2/pIsVIGVMEiOa3To7oqairq16xA=; b=cdnXCYOnuFAFYhYu4fplaasMAADG0ejeW9EvOMBWq0AdkHpb9W4lMzRuB5EIQufYdWAYE98+zVAHK+sCCJ7rbuz1wz/M4A5HAv8ughW9hDXN40zVmp2pPzNC3J1eCM+c1lhsRXOUSKb9fMU91/D7Y7uWW0E57ViRzlPyM9MXkg5qdLVGcraIFf+YfAB1Jm5nnmqNjRbqi2B1yeYEfnkZTqveDSm0bJ1C32b4RjS7fRAJRI2oqeEHwV0XvxKUH7j/298gQFn6Ea6GR1zU9/ajTZDWXj9jr6ss6bzCzDETs16u4FxTPwbKEy3dZblOyacd6lTEyBpbCOJDmpWOzBwNvw==
  • Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=C29iF97BXAAGfAWZVc1/91fYG0ROqg3mtdkU9tmDcmvI+PKcyqZG9svLvhHLnlbWJPjkHhZdA97aXxT6UrwdoWp/0DbgS2TkWKDEiuGlc+h5lyob0lHFjuMqjnZUYZmBoELj7obR4fihEZD86hJKxqaiQV7Y8OAZ5E9HXtCOm2KRdFeK2dC2N97f7qFK9+hgGHQv2uDa0QtAIIlah3UKguAmBSRRtYctvWM9AiGuD6mDVwVShamVGdymi5Hdtu+euvj8v23ROWDWviIK1ZRGRGvMbi9aunfZGGXztsaYNMpbxUqYWGJraED/z6bjCWUocbLugXnvCAGzfndHxETVDg==
  • Authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=suse.com;
  • Cc: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>, xen-devel@xxxxxxxxxxxxxxxxxxxx, Roger Pau Monne <roger.pau@xxxxxxxxxx>
  • Delivery-date: Thu, 17 Feb 2022 08:53:07 +0000
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>

On 16.02.2022 17:08, David Woodhouse wrote:
> On Wed, 2022-02-16 at 16:43 +0100, Jan Beulich wrote:
>> On 16.02.2022 11:30, Roger Pau Monne wrote:
>>> --- a/xen/include/public/arch-x86/cpuid.h
>>> +++ b/xen/include/public/arch-x86/cpuid.h
>>> @@ -102,6 +102,12 @@
>>>  #define XEN_HVM_CPUID_IOMMU_MAPPINGS   (1u << 2)
>>>  #define XEN_HVM_CPUID_VCPU_ID_PRESENT  (1u << 3) /* vcpu id is present in 
>>> EBX */
>>>  #define XEN_HVM_CPUID_DOMID_PRESENT    (1u << 4) /* domid is present in 
>>> ECX */
>>> +/*
>>> + * Bits 55:49 from the IO-APIC RTE and bits 11:5 from the MSI address can 
>>> be
>>> + * used to store high bits for the Destination ID. This expands the 
>>> Destination
>>> + * ID field from 8 to 15 bits, allowing to target APIC IDs up 32768.
>>> + */
>>> +#define XEN_HVM_CPUID_EXT_DEST_ID      (1u << 5)
>>
>> Would the comment perhaps better include "in the absence of (guest
>> visible) interrupt remapping", since otherwise the layout / meaning
>> changes anyway? Apart from this I'd be fine with this going in
>> ahead of the rest of this series.
> 
> No, this still works even if the guest has a vIOMMU with interrupt
> remapping. The Compatibility Format and Remappable Format MSI messages
> are distinct because the low bit of the Ext Dest ID is used to indicate
> Remappable Format.

Well, yes, that was my point: With that bit set bits 55:49 / 11:5 change
meaning. As an alternative to my initial proposal the comment could also
state that bit 48 / 4 needs to be clear for this feature to take effect.

Jan




 


Rackspace

Lists.xenproject.org is hosted with RackSpace, monitoring our
servers 24x7x365 and backed by RackSpace's Fanatical Support®.