[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH 1/3] VT-d: prune SAGAW recognition
- To: "Tian, Kevin" <kevin.tian@xxxxxxxxx>
- From: Jan Beulich <jbeulich@xxxxxxxx>
- Date: Wed, 24 Nov 2021 08:21:40 +0100
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=suse.com; dmarc=pass action=none header.from=suse.com; dkim=pass header.d=suse.com; arc=none
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=yFqVnAENQDllBUSyGSfZlLcMsiVQyNCRqsfLcJZhe/w=; b=b2/f7bWq9KduJF4WPO1j5Ph657Mp5E24IXJKmoDGq9TfsqiX6uWRTjSPOVHjCAZJwO6+btjlvrdriT0HqbPh1rDa74IQZ92Wb+E80l7GEIvBQ6tGdhQibPnpACMm5+1GnHtzq43l0o7yXyFjwCSxQDwGMT/Mb9RSwfEg9tx6STRQFDp2906nPo6v9lgMbm0Lzi/XAaYD7B4FPKG68XailSW/f3YTiTMoJtlYzFLVt2EWMXNYk2pxQBuEWPqma4yYgdKVP8lYgieouJkKqL/6apUstFD5aT0Es6d3nwAnrA8cTNtsQDspBM2neMrVi70NFb6OnWTDQrvxTYcv8BMSXA==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Oq3ZVjOOrNbsNTWcnzx8mPoIK8XCiPpOxzkrRM+u6ODQpIzTsQinl/HEacFBdKarChSOd6PmzgDqAgh4odrD6BA+CzsSYB0+MFu6aoJG8i9DX6H9Q8yydeSt3OTCdLmcPYbhUhXTDz4+Qaif2MLe8cPYpTyZ3JLJV6e821SP16HXfVyTbVQGw1ndPY8tLmZ28p6JjnrWcC3LZN+XYAweMCATACe/TzfmjFx7/bf3Di50fHao4G2J++2t/wIHIgf2Ka5+V+QT8LfS6E6WRdQKMb1+ju1jhAb1dyqQUEA5umzLQInZ07vGUimpmlN0xICbhqg58tdP+xUphIFK69eXew==
- Authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=suse.com;
- Cc: "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- Delivery-date: Wed, 24 Nov 2021 07:22:06 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 24.11.2021 02:22, Tian, Kevin wrote:
>> From: Jan Beulich <jbeulich@xxxxxxxx>
>> Sent: Tuesday, November 23, 2021 9:40 PM
>>
>> Bit 0 of the capability register field has become reserved at or before
>
> Bit 0 of 'SAGAW' in the capability register ...
I've changed it, but I thought the use of "field" in the sentence
together with the title would be entirely unambiguous.
>> spec version 2.2. Treat it as such. Replace the effective open-coding of
>> find_first_set_bit(). Adjust local variable types.
>>
>> Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
>> ---
>> Strictly speaking IOMMUs supporting only 3-level tables ought to result
>> in guests seeing a suitably reduced physical address width in CPUID.
>> And then the same would apply to restrictions resulting from MGAW.
>
> Yes. I remember there was some old discussion in Qemu community
> for whether guest physical addr width should be based on IOMMU
> constraints when passthrough device is used. But it didn't go anywhere
> (and I cannot find the link...)
I've added an item to my todo list.
> anyway with above comment fixed:
>
> Reviewed-by: Kevin Tian <kevin.tian@xxxxxxxxx>
Thanks.
Jan
|
