Re: [PATCH for-4.16 2/2] CHANGELOG: add missing entries for work during the 4.16 release cycle

[Bertrand Marquis <Bertrand.Marquis@xxxxxxx>]

Hi Roger,

> On 18 Nov 2021, at 10:37, Roger Pau Monné <roger.pau@xxxxxxxxxx> wrote:
> 
> On Thu, Nov 18, 2021 at 10:01:08AM +0000, Bertrand Marquis wrote:
>> Hi Roger,
>> 
>> 
>>> On 18 Nov 2021, at 08:58, Roger Pau Monné <roger.pau@xxxxxxxxxx> wrote:
>>> 
>>> On Wed, Nov 17, 2021 at 02:07:50PM +0000, Bertrand Marquis wrote:
>>>> Hi Roger,
>>>> 
>>>>> On 17 Nov 2021, at 09:53, Roger Pau Monne <roger.pau@xxxxxxxxxx> wrote:
>>>>> 
>>>>> Document some of the relevant changes during the 4.16 release cycle,
>>>>> likely more entries are missing.
>>>>> 
>>>>> Signed-off-by: Roger Pau Monné <roger.pau@xxxxxxxxxx>
>>>>> ---
>>>>> CHANGELOG.md | 11 +++++++++++
>>>>> 1 file changed, 11 insertions(+)
>>>>> 
>>>>> diff --git a/CHANGELOG.md b/CHANGELOG.md
>>>>> index ad1a8c2bc2..8b0bdd9cf0 100644
>>>>> --- a/CHANGELOG.md
>>>>> +++ b/CHANGELOG.md
>>>>> @@ -21,6 +21,17 @@ The format is based on [Keep a 
>>>>> Changelog](https://keepachangelog.com/en/1.0.0/)
>>>>> - qemu-traditional based device models (both, qemu-traditional and 
>>>>> ioemu-stubdom) will
>>>>>  no longer be built per default. In order to be able to use those, 
>>>>> configure needs to
>>>>>  be called with "--enable-qemu-traditional" as parameter.
>>>>> + - Fixes for credit2 scheduler stability in corner case conditions.
>>>>> + - Ongoing improvements in the hypervisor build system.
>>>>> + - vtpmmgr miscellaneous fixes in preparation for TPM 2.0 support.
>>>>> + - 32bit PV guests only supported in shim mode.
>>>>> + - Improved PVH dom0 debug key handling.
>>>>> + - Fix booting on some Intel systems without a PIT (i8254).
>>>> 
>>>> Missing:
>>>> - cpu ID sanitization on arm64
>>>> - fix 32/64bit vreg emulation on arm64
>>> 
>>> Can I get a bit more information about those items? Just a pointer to
>>> the commit messages would be helpful so that I can try to write a more
>>> comprehensive entry (or maybe it's just me not knowing anything about
>>> Arm that fails to understand it).
>> 
>> I agree, the text is not quite clear, I will try to come with a better one.
>> In the meantime here is are links to the series:
>> https://patchwork.kernel.org/project/xen-devel/list/?series=535805&state=*
>> https://patchwork.kernel.org/project/xen-devel/list/?series=477151&archive=both
> 
> Thanks. I've added:
> 
> - CPU feature leveling on arm64 platform with heterogeneous cores.
Yes
> - Handle register accesses as 32/64bit on Arm depending on the processor
>   bitness.

I would say:
- Fix coprocessor register accesses on Arm to use the proper 32/64bit access 
size.

Bertrand

> 
> Let me know if that's not accurate.
> 
> Roger.