[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v3 7/7] xen/arm: Activate TID3 in HCR_EL2
- To: Julien Grall <julien@xxxxxxx>
- From: Bertrand Marquis <Bertrand.Marquis@xxxxxxx>
- Date: Thu, 10 Dec 2020 15:36:28 +0000
- Accept-language: en-GB, en-US
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=KcRXd9RF3nGiJPD5Q9wbQ6foiJEShdxvoSLTCVIWw+Q=; b=U+8zBEkcOyCzazU8meIEQLVaOurams9nrNHzYKMeq6yfzHau7C4su/EgLoAqC0uJg1qj7rrE1ZR14MIrmoSCnOIqYuVLvbNLG5lE9lcYabK/3OUy1Cf/NNcvWugFstfw4UVrcD9mBmVJiv5LZtv1Xcupprek22b7aC0kk9U8NQy6jYr+feh7aClhB20RPpx1KlfV6JS43Im9pSlit3mbxRb7CFvOT5Se686xRvivzpu48PnGDwHx7YnsUVgKhncHh+owdiU0mJYUt9i69OaadjTEpkETZ59hsQioevbIt9c4of64EkMeD+3hkfIV167ftWKUZD9cebS0c6n4oKQIpA==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=k6a2CRPNzmfAVAxcGOSbp+Npl0L0/5j4kf0fMBoQni9BwKT2uUNu9VcXTJXwwzWrikV8u+Sn8DQAC53ig/y/S+LqcWVMu5D33a0qyVYBCHVzjop01VtGsEOFR+ZnggqgDwO6RB7KnvrLqqx5G7FHXUJaSnejw+ivTGPJrGdGq6Z0/LM/t2D8RfyRjmetH0Kx7feQJJuaJfzArlChINNFHTN9z85i3H7wGR1Nj+vFbEsPh/awDEbLdo3b3Bi0DaJpEB1VudAiYjGAkt18fH76QjFLonE2BBVJRIcGiaUr5+1dXLR39La8XGFuyZlMKc9zDOnKFwX4dkRpyYwtNTr0nQ==
- Authentication-results-original: xen.org; dkim=none (message not signed) header.d=none;xen.org; dmarc=none action=none header.from=arm.com;
- Cc: "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>, Stefano Stabellini <sstabellini@xxxxxxxxxx>, Volodymyr Babchuk <Volodymyr_Babchuk@xxxxxxxx>
- Delivery-date: Thu, 10 Dec 2020 15:36:46 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
- Nodisclaimer: true
- Original-authentication-results: xen.org; dkim=none (message not signed) header.d=none;xen.org; dmarc=none action=none header.from=arm.com;
- Thread-index: AQHWzkl013/0PfAuCEKW6HlWdTiWa6nvZnoAgAERZAA=
- Thread-topic: [PATCH v3 7/7] xen/arm: Activate TID3 in HCR_EL2
Hi Julien,
> On 9 Dec 2020, at 23:17, Julien Grall <julien@xxxxxxx> wrote:
>
> Hi Bertrand,
>
> On 09/12/2020 16:31, Bertrand Marquis wrote:
>> Activate TID3 bit in HSR register when starting a guest.
>
> s/HSR/HCR/
>
Right, I did it a lot thanks for the review.
I will fix that in V4.
>> This will trap all coprecessor ID registers so that we can give to guest
>> values corresponding to what they can actually use and mask some
>> features to guests even though they would be supported by the underlying
>> hardware (like SVE or MPAM).
>
> So this will make sure the guest will not be able to identify the feature.
> Did you check that the features are effectively not accessible by the guest?
> IOW it should trap.
For SVE yes I checked and with the serie a Linux kernel with SVE support
activated on a target with SVE is now working (was crashing before).
For MPAM, I have no target available with MPAM support so I could not test that
but your recent XSA patch did turn the access to the guest off.
With my SVE test, I could confirm that access are trapped and properly emulated.
Cheers
Bertrand
>
> Cheers,
>
> --
> Julien Grall
>
|
