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Re: [PATCH] xen/arm: Add workaround for Cortex-A55 erratum #1530923





On 24/11/2020 17:44, Stefano Stabellini wrote:
On Tue, 24 Nov 2020, Rahul Singh wrote:
On 24 Nov 2020, at 11:12 am, Bertrand Marquis <Bertrand.Marquis@xxxxxxx> wrote:

On the Cortex A55, TLB entries can be allocated by a speculative AT
instruction. If this is happening during a guest context switch with an
inconsistent page table state in the guest, TLBs with wrong values might
be allocated.
The ARM64_WORKAROUND_AT_SPECULATE workaround is used as for erratum
1165522 on Cortex A76 or Neoverse N1.

This change is also introducing the MIDR identifier for the Cortex-A55.

Signed-off-by: Bertrand Marquis <bertrand.marquis@xxxxxxx>

Reviewed-by: Rahul Singh <rahul.singh@xxxxxxx>

Reviewed-by: Stefano Stabellini <sstabellini@xxxxxxxxxx>

Acked-by: Julien Grall <jgrall@xxxxxxxxxx>

And committed.

Cheers,

--
Julien Grall



 


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