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Re: [PATCH 08/10] vpci/arm: Allow updating BAR's header for non-ECAM bridges
- To: Jan Beulich <jbeulich@xxxxxxxx>, Oleksandr Andrushchenko <andr2000@xxxxxxxxx>
- From: Oleksandr Andrushchenko <Oleksandr_Andrushchenko@xxxxxxxx>
- Date: Fri, 13 Nov 2020 10:55:13 +0000
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- Thread-topic: [PATCH 08/10] vpci/arm: Allow updating BAR's header for non-ECAM bridges
On 11/13/20 12:47 PM, Jan Beulich wrote:
> On 13.11.2020 11:39, Oleksandr Andrushchenko wrote:
>> On 11/13/20 12:29 PM, Jan Beulich wrote:
>>> On 09.11.2020 13:50, Oleksandr Andrushchenko wrote:
>>>> From: Oleksandr Andrushchenko <oleksandr_andrushchenko@xxxxxxxx>
>>>>
>>>> Non-ECAM host bridges in hwdom go directly to PCI config space,
>>>> not through vpci (they use their specific method for accessing PCI
>>>> configuration, e.g. dedicated registers etc.).
>>> And access to these dedicated registers can't be intercepted?
>> It can. But then you have to fully emulate that bridge, e.g.
>>
>> "if we write A to regB and after that write C to regZ then it
>>
>> means we are accessing config space. If we write...."
> Sounds pretty much like the I/O port based access mechanism on
> x86, which also has some sort of "enable". Of course, I/O port
> accesses are particularly easy to intercept and handle...
Yes, it has somewhat similar idea
>
>> I mean this would need lots of code in Xen to achieve that
> Possibly, but look at the amount of code we have in Xen on the
> x86 side to handle MCFG writes by Dom0.
But MCFG is handled the same way for all x86 machines, right?
And here I'll have to have a SoC specific code, e.g. a specific driver
>
> Jan
Thank you,
Oleksandr
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