[PATCH] x86: avoid HPET use also on certain Coffee Lake H

[Jan Beulich <jbeulich@xxxxxxxx>]

Linux commit f8edbde885bbcab6a2b4a1b5ca614e6ccb807577 says

"Coffee Lake H SoC has similar behavior as Coffee Lake, skewed HPET
 timer once the SoCs entered PC10."

Again follow this for Xen as well, noting though that even the
pre-existing PCI ID refers to a H-processor line variant (the 6-core
one). It is also suspicious that the datasheet names 0x3e10 for the
4-core variant, while the Linux commit specifies 0x3e20, which I haven't
been able to locate in any datasheet yet. To be on the safe side, add
both until clarification can be provided by Intel.

Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>

--- a/xen/arch/x86/time.c
+++ b/xen/arch/x86/time.c
@@ -397,10 +397,16 @@ static int64_t __init init_hpet(struct p
          * entered PC10.
          */
         if ( pci_conf_read16(PCI_SBDF(0, 0, 0, 0),
-                             PCI_VENDOR_ID) == PCI_VENDOR_ID_INTEL &&
-             pci_conf_read16(PCI_SBDF(0, 0, 0, 0),
-                             PCI_DEVICE_ID) == 0x3ec4 )
-            hpet_address = 0;
+                             PCI_VENDOR_ID) == PCI_VENDOR_ID_INTEL )
+            switch ( pci_conf_read16(PCI_SBDF(0, 0, 0, 0),
+                                     PCI_DEVICE_ID) )
+            {
+            case 0x3e10: /* as per datasheet (4 core variant) */
+            case 0x3e20: /* as per respective Linux commit */
+            case 0x3ec4:
+                hpet_address = 0;
+                break;
+            }
 
         if ( !hpet_address )
             printk("Disabling HPET for being unreliable\n");