[Xen-devel] [PATCH v5 0/4] x86/HVM: implement memory read caching

[Jan Beulich <jbeulich@xxxxxxxx>]

Emulation requiring device model assistance uses a form of instruction
re-execution, assuming that the second (and any further) pass takes
exactly the same path. This is a valid assumption as far as use of CPU
registers goes (as those can't change without any other instruction
executing in between), but is wrong for memory accesses. In particular
it has been observed that Windows might page out buffers underneath
an instruction currently under emulation (hitting between two passes).
If the first pass translated a linear address successfully, any subsequent
pass needs to do so too, yielding the exact same translation.

Introduce a cache to make sure above described assumption holds. This
is a very simplistic implementation for now: Only exact matches are
satisfied (no overlaps or partial reads or anything).

There's also some perhaps seemingly unrelated cleanup here which was
found desirable on the way - the 3 initial patches are truly prereqs
(at least in a contextual way), while the 2 last ones are just for
things noticed along the way.

1: x86/HVM: cancel emulation when register state got altered
2: x86/HVM: implement memory read caching for insn emulation
3: x86/mm: use cache in guest_walk_tables()
4: x86/HVM: __hvm_copy()'s size parameter is an unsigned quantity

The main difference to v4 are the new first and last patches (with
the latter being largely unrelated cleanup). For other changes see
the individual patches.

Jan

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