Re: [Xen-devel] [PATCH] xen/arm: Implement GICD_IGRPMODR as RAZ/WI for VGICv3

[Jeff Kubascik <jeff.kubascik@xxxxxxxxxxxxxxx>]

Hello Julien,

On 1/29/2020 4:27 PM, Julien Grall wrote:
> Hi Jeff,
> 
> On 21/01/2020 14:39, Jeff Kubascik wrote:
>> The VGICv3 module does not implement security extensions for guests.
>> Furthermore, per the ARM Generic Interrupt Controller Architecture
>> Specification (ARM IHI 0069E), section 9.9.15, the GICD_IGRPMODR
>> register should be RAZ/WI to non-secure accesses when GICD_CTLR.DS = 0.
>> This implements the GICD_IGRPMODR register for guest VMs as RAZ/WI, to
>> avoid a data abort in the case the guest attempts to read or write the
>> register.
> 
> Per the spec, all reserved registers should be RAZ/WI. So how about
> implementing the default case as read_as_zero/write_ignore?
> 
> This would also cover some problem that may arise with future Linux. I
> have actually been told that Linux will access registers (IIRC GICv4
> specific) that may not have been implemented by Xen and should be RAZ/WI.

I am very much in support of this approach. We have seen this issue in the past
when porting other RTOS's to Xen, typically during GIC driver initialization.

I'll send out a v2 of this patch that will make the default case RAZ/WI.

> Cheers,
> 
> --
> Julien Grall
> 

Sincerely,
Jeff Kubascik

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