Re: [Xen-devel] [PATCH for-4.13 2/2] x86/ioapic: don't use raw entry reads/writes in clear_IO_APIC_pin

[Roger Pau Monné <roger.pau@xxxxxxxxxx>]

On Thu, Nov 07, 2019 at 04:46:32PM +0100, Roger Pau Monné wrote:
> On Thu, Nov 07, 2019 at 04:28:56PM +0100, Jan Beulich wrote:
> > On 07.11.2019 16:06, Roger Pau Monne wrote:
> > > clear_IO_APIC_pin can be called after the iommu has been enabled, and
> > > using raw entry reads and writes will result in a misconfiguration of
> > > the entries already setup to use the interrupt remapping table.
> > 
> > I'm afraid I don't understand this: Raw reads and writes don't even
> > go to the IOMMU interrupt remapping code, so how would the assertion
> > be triggered?
> 
> Because the code does something like:
> 
> memset(&rte, 0, ...);
> ...
> __ioapic_write_entry(apic, pin, true, rte);
> 
> At which point you misconfigure an ioapic entry that was already setup
> to point to an interrupt remapping entry, and the AMD IOMMU code
> chokes in the assert below.

Just to clarify since I think my reply hasn't been fully clear, the
ASSERT doesn't trigger in clear_IO_APIC_pin, but at a later point when
the IO-APIC entry is configured.

Thanks, Roger.

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