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[Xen-devel] [PATCH v5 01/15] x86/cpu: Create Hygon Dhyana architecture support file



Add x86 architecture support for a new processor: Hygon Dhyana Family
18h. To make Hygon initialization flow more clear, carve out code from
amd.c into a separate file hygon.c, and remove unnecessary code for
Hygon Dhyana.

To identify Hygon Dhyana CPU, add a new vendor type X86_VENDOR_HYGON
and vendor ID "HygonGenuine" for system recognition, and fit the new
x86 vendor lookup mechanism.

Hygon can fully use the function early_init_amd(), so make this common
function non-static and direct call it from Hygon code.

Add a separate hygon_get_topology(), which calculate phys_proc_id from
AcpiId[6](see reference [1]).

Reference:
[1] https://git.kernel.org/tip/e0ceeae708cebf22c990c3d703a4ca187dc837f5

Signed-off-by: Pu Wen <puwen@xxxxxxxx>
---
 xen/arch/x86/cpu/Makefile         |   1 +
 xen/arch/x86/cpu/amd.c            |   2 +-
 xen/arch/x86/cpu/common.c         |   1 +
 xen/arch/x86/cpu/cpu.h            |   3 +
 xen/arch/x86/cpu/hygon.c          | 114 ++++++++++++++++++++++++++++++++++++++
 xen/include/asm-x86/x86-vendors.h |   7 ++-
 xen/lib/x86/cpuid.c               |   6 ++
 7 files changed, 132 insertions(+), 2 deletions(-)
 create mode 100644 xen/arch/x86/cpu/hygon.c

diff --git a/xen/arch/x86/cpu/Makefile b/xen/arch/x86/cpu/Makefile
index 34a01ca..466acc8 100644
--- a/xen/arch/x86/cpu/Makefile
+++ b/xen/arch/x86/cpu/Makefile
@@ -4,6 +4,7 @@ subdir-y += mtrr
 obj-y += amd.o
 obj-y += centaur.o
 obj-y += common.o
+obj-y += hygon.o
 obj-y += intel.o
 obj-y += intel_cacheinfo.o
 obj-y += mwait-idle.o
diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index 7a73d62..6554d5d 100644
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -526,7 +526,7 @@ static void amd_get_topology(struct cpuinfo_x86 *c)
                                                           : c->cpu_core_id);
 }
 
-static void early_init_amd(struct cpuinfo_x86 *c)
+void early_init_amd(struct cpuinfo_x86 *c)
 {
        if (c == &boot_cpu_data)
                amd_init_levelling();
diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
index b2249b5..74c9426 100644
--- a/xen/arch/x86/cpu/common.c
+++ b/xen/arch/x86/cpu/common.c
@@ -691,6 +691,7 @@ void __init early_cpu_init(void)
        amd_init_cpu();
        centaur_init_cpu();
        shanghai_init_cpu();
+       hygon_init_cpu();
        early_cpu_detect();
 }
 
diff --git a/xen/arch/x86/cpu/cpu.h b/xen/arch/x86/cpu/cpu.h
index edc88b1..c3ae2ee 100644
--- a/xen/arch/x86/cpu/cpu.h
+++ b/xen/arch/x86/cpu/cpu.h
@@ -16,7 +16,10 @@ extern unsigned int opt_cpuid_mask_ext_ecx, 
opt_cpuid_mask_ext_edx;
 extern int get_model_name(struct cpuinfo_x86 *c);
 extern void display_cacheinfo(struct cpuinfo_x86 *c);
 
+void early_init_amd(struct cpuinfo_x86 *c);
+
 int intel_cpu_init(void);
 int amd_init_cpu(void);
 int centaur_init_cpu(void);
 int shanghai_init_cpu(void);
+int hygon_init_cpu(void);
diff --git a/xen/arch/x86/cpu/hygon.c b/xen/arch/x86/cpu/hygon.c
new file mode 100644
index 0000000..912849c
--- /dev/null
+++ b/xen/arch/x86/cpu/hygon.c
@@ -0,0 +1,114 @@
+#include <xen/init.h>
+#include <asm/processor.h>
+#include <asm/hvm/support.h>
+#include <asm/spec_ctrl.h>
+
+#include "cpu.h"
+
+#define APICID_SOCKET_ID_BIT 6
+
+static void hygon_get_topology(struct cpuinfo_x86 *c)
+{
+       unsigned int ebx;
+
+       if (c->x86_max_cores <= 1)
+               return;
+
+       /* Socket ID is ApicId[6] for Hygon processors. */
+       c->phys_proc_id >>= APICID_SOCKET_ID_BIT;
+
+       ebx = cpuid_ebx(0x8000001e);
+       c->x86_num_siblings = ((ebx >> 8) & 0x3) + 1;
+       c->x86_max_cores /= c->x86_num_siblings;
+       c->cpu_core_id = ebx & 0xff;
+
+       if (opt_cpu_info)
+               printk("CPU %d(%d) -> Processor %d, Core %d\n",
+                       smp_processor_id(), c->x86_max_cores,
+                               c->phys_proc_id, c->cpu_core_id);
+}
+
+static void init_hygon(struct cpuinfo_x86 *c)
+{
+       unsigned long long value;
+
+       /*
+        * Attempt to set lfence to be Dispatch Serialising.  This MSR almost
+        * certainly isn't virtualised (and Xen at least will leak the real
+        * value in but silently discard writes), as well as being per-core
+        * rather than per-thread, so do a full safe read/write/readback cycle
+        * in the worst case.
+        */
+       if (rdmsr_safe(MSR_AMD64_DE_CFG, value))
+               /* Unable to read.  Assume the safer default. */
+               __clear_bit(X86_FEATURE_LFENCE_DISPATCH,
+                           c->x86_capability);
+       else if (value & AMD64_DE_CFG_LFENCE_SERIALISE)
+               /* Already dispatch serialising. */
+               __set_bit(X86_FEATURE_LFENCE_DISPATCH,
+                         c->x86_capability);
+       else if (wrmsr_safe(MSR_AMD64_DE_CFG,
+                           value | AMD64_DE_CFG_LFENCE_SERIALISE) ||
+                rdmsr_safe(MSR_AMD64_DE_CFG, value) ||
+                !(value & AMD64_DE_CFG_LFENCE_SERIALISE))
+               /* Attempt to set failed.  Assume the safer default. */
+               __clear_bit(X86_FEATURE_LFENCE_DISPATCH,
+                           c->x86_capability);
+       else
+               /* Successfully enabled! */
+               __set_bit(X86_FEATURE_LFENCE_DISPATCH,
+                         c->x86_capability);
+
+       /*
+        * If the user has explicitly chosen to disable Memory Disambiguation
+        * to mitigiate Speculative Store Bypass, poke the appropriate MSR.
+        */
+       if (opt_ssbd && !rdmsr_safe(MSR_AMD64_LS_CFG, value)) {
+               value |= 1ull << 10;
+               wrmsr_safe(MSR_AMD64_LS_CFG, value);
+       }
+
+       /* MFENCE stops RDTSC speculation */
+       if (!cpu_has_lfence_dispatch)
+               __set_bit(X86_FEATURE_MFENCE_RDTSC, c->x86_capability);
+
+       display_cacheinfo(c);
+
+       if (c->extended_cpuid_level >= 0x80000008)
+               c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;
+
+       if (c->extended_cpuid_level >= 0x80000007) {
+               if (cpu_has(c, X86_FEATURE_ITSC)) {
+                       __set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
+                       __set_bit(X86_FEATURE_NONSTOP_TSC, c->x86_capability);
+                       __set_bit(X86_FEATURE_TSC_RELIABLE, c->x86_capability);
+               }
+       }
+
+       hygon_get_topology(c);
+
+       /* Hygon CPUs do not support SYSENTER outside of legacy mode. */
+       __clear_bit(X86_FEATURE_SEP, c->x86_capability);
+
+       /* Hygon processors have APIC timer running in deep C states. */
+       if (opt_arat)
+               __set_bit(X86_FEATURE_ARAT, c->x86_capability);
+
+       if (cpu_has(c, X86_FEATURE_EFRO)) {
+               rdmsrl(MSR_K7_HWCR, value);
+               value |= (1 << 27); /* Enable read-only APERF/MPERF bit */
+               wrmsrl(MSR_K7_HWCR, value);
+       }
+}
+
+static const struct cpu_dev hygon_cpu_dev = {
+       .c_vendor       = "Hygon",
+       .c_early_init   = early_init_amd,
+       .c_init         = init_hygon,
+};
+
+int __init hygon_init_cpu(void)
+{
+       cpu_devs[X86_VENDOR_HYGON] = &hygon_cpu_dev;
+       return 0;
+}
diff --git a/xen/include/asm-x86/x86-vendors.h 
b/xen/include/asm-x86/x86-vendors.h
index 774ceac..75fefcf 100644
--- a/xen/include/asm-x86/x86-vendors.h
+++ b/xen/include/asm-x86/x86-vendors.h
@@ -30,6 +30,11 @@
 #define X86_VENDOR_SHANGHAI_ECX 0x20206961U
 #define X86_VENDOR_SHANGHAI_EDX 0x68676e61U
 
-#define X86_VENDOR_NUM 5
+#define X86_VENDOR_HYGON 5
+#define X86_VENDOR_HYGON_EBX 0x6f677948 /* "HygonGenuine" */
+#define X86_VENDOR_HYGON_ECX 0x656e6975
+#define X86_VENDOR_HYGON_EDX 0x6e65476e
+
+#define X86_VENDOR_NUM 6
 
 #endif /* __XEN_X86_VENDORS_H__ */
diff --git a/xen/lib/x86/cpuid.c b/xen/lib/x86/cpuid.c
index 311d19e..d0b3ff7 100644
--- a/xen/lib/x86/cpuid.c
+++ b/xen/lib/x86/cpuid.c
@@ -29,6 +29,12 @@ unsigned int x86_cpuid_lookup_vendor(uint32_t ebx, uint32_t 
ecx, uint32_t edx)
              edx == X86_VENDOR_SHANGHAI_EDX )
             return X86_VENDOR_SHANGHAI;
         break;
+
+    case X86_VENDOR_HYGON_EBX:
+        if ( ecx == X86_VENDOR_HYGON_ECX &&
+             edx == X86_VENDOR_HYGON_EDX )
+            return X86_VENDOR_HYGON;
+        break;
     }
 
     return X86_VENDOR_UNKNOWN;
-- 
2.7.4


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