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Re: [Xen-devel] [PATCH v2] x86/nmi: correctly check MSB of P6 performance counter MSR in watchdog

On 26/02/2019 14:56, Jan Beulich wrote:
>>>> On 26.02.19 at 14:33, <igor.druzhinin@xxxxxxxxxx> wrote:
>> On 26/02/2019 13:12, Igor Druzhinin wrote:
>>> @@ -292,6 +295,7 @@ static inline void write_watchdog_counter(const char 
>>> *descr)
>>>      u64 count = (u64)cpu_khz * 1000;
>>>      do_div(count, nmi_hz);
>>> +    count = min(count, (1UL << (nmi_p6_event_width - 1)) - 1);
>>>      if(descr)
>>>          Dprintk("setting %s to -%#"PRIx64"\n", descr, count);
>>>      wrmsrl(nmi_perfctr_msr, 0 - count);
>> I mistakenly used nmi_p6_event_width in a shared call for all
>> architectures - I'll fix it in v3.
> But is clipping the count valid at all, no matter where you do it?
> Won't the NMI get raised earlier than expected then? Wouldn't
> it rather be nmi_hz that would then need changing if count
> ends up to large?

From my understanding, the logic is that we're trying our best to make
the delay between ticks as long as possible but not longer than 0.5 sec.
This, of course, works only if the invariant of the highest bit being 1
is preserved.

Although, I wouldn't mind to drop this part since it basically worked
before even without clipping.


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