Re: [Xen-devel] [PATCH 09/15] x86/pv: Add Hygon Dhyana support to emulate MSRs access

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 30.01.19 at 10:52, <puwen@xxxxxxxx> wrote:
> On 2019/1/26 1:48, Jan Beulich wrote:
>>>>> On 20.12.18 at 14:14, <puwen@xxxxxxxx> wrote:
>>> The Hygon Dhyana CPU supports lots of MSRs(such as perf event select and
>>> counter MSRs, hardware configuration MSR, MMIO configuration base address
>>> MSR, MPERF/APERF MSRs) as AMD CPU does, so add Hygon Dhyana support to the
>>> PV emulation infrastructure by using the code path of AMD.
>>>
>>> As hygon.c needs to write the load-store configuration(LS_CFG) MSR, so add
>>> new case in write_msr to handle this situation.
>> 
>> Which hygon.c do you mean here? This addition, if valid at all, clearly
> 
> I mean hygon.c from the linux kernel. But in fact it's some other kernel
> part will write LS_CFG MSR. So the description will be refined.
> 
>> needs its own patch and justification, the more that you permit access
> 
> This addition is needed, otherwise there will be warnings like:
> "(XEN) emul-priv-op.c:1165:d0v12 Domain attempted WRMSR c0011020 from 
> 0x0206800000000000 to 0x0206800000000400"

But that's an issue to be taken care of in kernel code, not by
making Xen permit the write. There are other MSRs where the
kernel similarly tries accesses which it shouldn't try when run in
PV mode.

Jan



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