[Xen-devel] [PATCH 04/15] x86/cpu/mce: Add Hygon Dhyana support to the MCA infrastructure

[Pu Wen <puwen@xxxxxxxx>]

The machine check architecture for Hygon Dhyana CPU is similar to the
AMD family 17h one. Add vendor checking for Hygon Dhyana to share the
code path of AMD family 17h.

Signed-off-by: Pu Wen <puwen@xxxxxxxx>
---
 xen/arch/x86/cpu/common.c              | 3 ++-
 xen/arch/x86/cpu/mcheck/amd_nonfatal.c | 5 +++--
 xen/arch/x86/cpu/mcheck/mce.c          | 6 ++++--
 xen/arch/x86/cpu/mcheck/mce_amd.c      | 3 ++-
 xen/arch/x86/cpu/mcheck/non-fatal.c    | 3 ++-
 xen/arch/x86/cpu/mcheck/vmce.c         | 2 ++
 6 files changed, 15 insertions(+), 7 deletions(-)

diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
index ce48d4a..41fbcff 100644
--- a/xen/arch/x86/cpu/common.c
+++ b/xen/arch/x86/cpu/common.c
@@ -345,7 +345,8 @@ static void __init early_cpu_detect(void)
                        hap_paddr_bits = PADDR_BITS;
        }
 
-       if (c->x86_vendor != X86_VENDOR_AMD)
+       if (c->x86_vendor != X86_VENDOR_AMD &&
+           c->x86_vendor != X86_VENDOR_HYGON)
                park_offline_cpus = opt_mce;
 
        initialize_cpu_data(0);
diff --git a/xen/arch/x86/cpu/mcheck/amd_nonfatal.c 
b/xen/arch/x86/cpu/mcheck/amd_nonfatal.c
index 222f539..589dac5 100644
--- a/xen/arch/x86/cpu/mcheck/amd_nonfatal.c
+++ b/xen/arch/x86/cpu/mcheck/amd_nonfatal.c
@@ -203,10 +203,11 @@ static void mce_amd_work_fn(void *data)
 
 void __init amd_nonfatal_mcheck_init(struct cpuinfo_x86 *c)
 {
-       if (c->x86_vendor != X86_VENDOR_AMD)
+       if (c->x86_vendor != X86_VENDOR_AMD &&
+           c->x86_vendor != X86_VENDOR_HYGON)
                return;
 
-       /* Assume we are on K8 or newer AMD CPU here */
+       /* Assume we are on K8 or newer AMD or Hygon CPU here */
 
        /* The threshold bitfields in MSR_IA32_MC4_MISC has
         * been introduced along with the SVME feature bit. */
diff --git a/xen/arch/x86/cpu/mcheck/mce.c b/xen/arch/x86/cpu/mcheck/mce.c
index 30cdb06..822650b 100644
--- a/xen/arch/x86/cpu/mcheck/mce.c
+++ b/xen/arch/x86/cpu/mcheck/mce.c
@@ -777,6 +777,7 @@ void mcheck_init(struct cpuinfo_x86 *c, bool bsp)
 
     switch ( c->x86_vendor )
     {
+    case X86_VENDOR_HYGON:
     case X86_VENDOR_AMD:
         inited = amd_mcheck_init(c);
         break;
@@ -1172,10 +1173,11 @@ static bool x86_mc_msrinject_verify(struct 
xen_mc_msrinject *mci)
 
             /* MSRs that the HV will take care of */
             case MSR_K8_HWCR:
-                if ( c->x86_vendor == X86_VENDOR_AMD )
+                if ( c->x86_vendor == X86_VENDOR_AMD ||
+                     c->x86_vendor == X86_VENDOR_HYGON )
                     reason = "HV will operate HWCR";
                 else
-                    reason = "only supported on AMD";
+                    reason = "only supported on AMD or Hygon";
                 break;
 
             default:
diff --git a/xen/arch/x86/cpu/mcheck/mce_amd.c 
b/xen/arch/x86/cpu/mcheck/mce_amd.c
index d125bc1..9c9cbd1 100644
--- a/xen/arch/x86/cpu/mcheck/mce_amd.c
+++ b/xen/arch/x86/cpu/mcheck/mce_amd.c
@@ -162,7 +162,8 @@ mcequirk_lookup_amd_quirkdata(struct cpuinfo_x86 *c)
 {
     int i;
 
-    BUG_ON(c->x86_vendor != X86_VENDOR_AMD);
+    if (c->x86_vendor != X86_VENDOR_AMD)
+        return 0;
 
     for ( i = 0; i < ARRAY_SIZE(mce_amd_quirks); i++ )
     {
diff --git a/xen/arch/x86/cpu/mcheck/non-fatal.c 
b/xen/arch/x86/cpu/mcheck/non-fatal.c
index d12e8f2..56f1f0d 100644
--- a/xen/arch/x86/cpu/mcheck/non-fatal.c
+++ b/xen/arch/x86/cpu/mcheck/non-fatal.c
@@ -100,8 +100,9 @@ static int __init init_nonfatal_mce_checker(void)
         * Check for non-fatal errors every MCE_RATE s
         */
        switch (c->x86_vendor) {
+       case X86_VENDOR_HYGON:
        case X86_VENDOR_AMD:
-               /* Assume we are on K8 or newer AMD CPU here */
+               /* Assume we are on K8 or newer AMD or Hygon CPU here */
                amd_nonfatal_mcheck_init(c);
                break;
 
diff --git a/xen/arch/x86/cpu/mcheck/vmce.c b/xen/arch/x86/cpu/mcheck/vmce.c
index f15835e..da1b007 100644
--- a/xen/arch/x86/cpu/mcheck/vmce.c
+++ b/xen/arch/x86/cpu/mcheck/vmce.c
@@ -153,6 +153,7 @@ static int bank_mce_rdmsr(const struct vcpu *v, uint32_t 
msr, uint64_t *val)
             ret = vmce_intel_rdmsr(v, msr, val);
             break;
 
+        case X86_VENDOR_HYGON:
         case X86_VENDOR_AMD:
             ret = vmce_amd_rdmsr(v, msr, val);
             break;
@@ -283,6 +284,7 @@ static int bank_mce_wrmsr(struct vcpu *v, uint32_t msr, 
uint64_t val)
             ret = vmce_intel_wrmsr(v, msr, val);
             break;
 
+        case X86_VENDOR_HYGON:
         case X86_VENDOR_AMD:
             ret = vmce_amd_wrmsr(v, msr, val);
             break;
-- 
2.7.4


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