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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH 4/9] x86/amd: Introduce CPUID/MSR definitions for per-vcpu SSBD support
At the time of writing, the spec is available from: https://developer.amd.com/wp-content/resources/124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf Future hardware (Zen v2) is expect to have hardware MSR_SPEC_CTRL support, including SPEC_CTRL.SSBD, and with the expectation that this will be directly passed through to guests for performance. On currently released hardware, the only mechanism available is the legacy LS_CFG option, and this is very expensive to use. Furthermore, emulating MSR_SPEC_CTRL via interception is prohibitively expensive, as certain OSes use the write-discard flexibility to simplify their entry/exit logic. As an alternative, MSR_VIRT_SPEC_CTRL is specified as an architectural control (with semantics equivilent to MSR_SPEC_CTRL) which is provided by the hypervisor. This abstracts away the model-specific details of the LS_CFG mechanism, which allows migration safety to be retained. Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx> --- CC: Jan Beulich <JBeulich@xxxxxxxx> CC: Wei Liu <wei.liu2@xxxxxxxxxx> CC: Roger Pau Monné <roger.pau@xxxxxxxxxx> CC: Brian Woods <brian.woods@xxxxxxx> --- tools/libxl/libxl_cpuid.c | 5 +++++ tools/misc/xen-cpuid.c | 4 ++++ xen/arch/x86/spec_ctrl.c | 7 ++++++- xen/include/asm-x86/msr-index.h | 3 +++ xen/include/public/arch-x86/cpufeatureset.h | 5 +++++ 5 files changed, 23 insertions(+), 1 deletion(-) diff --git a/tools/libxl/libxl_cpuid.c b/tools/libxl/libxl_cpuid.c index 52e16c2..51eb41c 100644 --- a/tools/libxl/libxl_cpuid.c +++ b/tools/libxl/libxl_cpuid.c @@ -245,6 +245,11 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str) {"invtsc", 0x80000007, NA, CPUID_REG_EDX, 8, 1}, {"ibpb", 0x80000008, NA, CPUID_REG_EBX, 12, 1}, + {"amd_ibrs", 0x80000008, NA, CPUID_REG_EBX, 14, 1}, + {"amd_stibp", 0x80000008, NA, CPUID_REG_EBX, 15, 1}, + {"amd_ssbd", 0x80000008, NA, CPUID_REG_EBX, 24, 1}, + {"virt_sc_ssbd", 0x80000008, NA, CPUID_REG_EBX, 25, 1}, + {"amd_ssb_no", 0x80000008, NA, CPUID_REG_EBX, 26, 1}, {"nc", 0x80000008, NA, CPUID_REG_ECX, 0, 8}, {"apicidsize", 0x80000008, NA, CPUID_REG_ECX, 12, 4}, diff --git a/tools/misc/xen-cpuid.c b/tools/misc/xen-cpuid.c index 6e7ca8b..efb789e 100644 --- a/tools/misc/xen-cpuid.c +++ b/tools/misc/xen-cpuid.c @@ -140,6 +140,10 @@ static const char *str_e8b[32] = [ 0] = "clzero", [12] = "ibpb", + [14] = "amd_ibrs", [15] = "amd_stibp", + + [24] = "amd_ssbd", [25] = "virt_sc_ssbd", + [26] = "amd_ssb_no", }; static const char *str_7d0[32] = diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c index a36bcef..af92866 100644 --- a/xen/arch/x86/spec_ctrl.c +++ b/xen/arch/x86/spec_ctrl.c @@ -224,12 +224,17 @@ static void __init print_details(enum ind_thunk thunk, uint64_t caps) printk("Speculative mitigation facilities:\n"); /* Hardware features which pertain to speculative mitigations. */ - printk(" Hardware features:%s%s%s%s%s%s%s%s%s%s\n", + printk(" Hardware features:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", (_7d0 & cpufeat_mask(X86_FEATURE_IBRSB)) ? " IBRS/IBPB" : "", (_7d0 & cpufeat_mask(X86_FEATURE_STIBP)) ? " STIBP" : "", (_7d0 & cpufeat_mask(X86_FEATURE_L1D_FLUSH)) ? " L1D_FLUSH" : "", (_7d0 & cpufeat_mask(X86_FEATURE_SSBD)) ? " SSBD" : "", (e8b & cpufeat_mask(X86_FEATURE_IBPB)) ? " IBPB" : "", + (e8b & cpufeat_mask(X86_FEATURE_AMD_IBRS)) ? " IBRS" : "", + (e8b & cpufeat_mask(X86_FEATURE_AMD_STIBP)) ? " AMD_STIBP" : "", + (e8b & cpufeat_mask(X86_FEATURE_AMD_SSBD)) ? " AMD_IBPB" : "", + (e8b & cpufeat_mask(X86_FEATURE_VIRT_SC_SSBD)) ? " VIRT_SSBD" : "", + (e8b & cpufeat_mask(X86_FEATURE_AMD_SSB_NO)) ? " SSB_NO" : "", (caps & ARCH_CAPABILITIES_IBRS_ALL) ? " IBRS_ALL" : "", (caps & ARCH_CAPABILITIES_RDCL_NO) ? " RDCL_NO" : "", (caps & ARCH_CAPS_RSBA) ? " RSBA" : "", diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h index 3faed27..56346d7 100644 --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -202,6 +202,9 @@ #define MSR_K8_VM_CR 0xc0010114 #define MSR_K8_VM_HSAVE_PA 0xc0010117 +/* Bit layout expected to match MSR_SPEC_CTRL */ +#define MSR_VIRT_SPEC_CTRL 0xc001011f + #define MSR_AMD_FAM15H_EVNTSEL0 0xc0010200 #define MSR_AMD_FAM15H_PERFCTR0 0xc0010201 #define MSR_AMD_FAM15H_EVNTSEL1 0xc0010202 diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h index 6c82816..8f80195 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -238,6 +238,11 @@ XEN_CPUFEATURE(EFRO, 7*32+10) /* APERF/MPERF Read Only interface */ /* AMD-defined CPU features, CPUID level 0x80000008.ebx, word 8 */ XEN_CPUFEATURE(CLZERO, 8*32+ 0) /*A CLZERO instruction */ XEN_CPUFEATURE(IBPB, 8*32+12) /*A IBPB support only (no IBRS, used by AMD) */ +XEN_CPUFEATURE(AMD_IBRS, 8*32+14) /* MSR_SPEC_CTRL.IBRS available */ +XEN_CPUFEATURE(AMD_STIBP, 8*32+15) /* MSR_SPEC_CTRL.STIBP available */ +XEN_CPUFEATURE(AMD_SSBD, 8*32+24) /* MSR_SPEC_CTRL.SSBD available */ +XEN_CPUFEATURE(VIRT_SC_SSBD, 8*32+25) /* MSR_VIRT_SPEC_CTRL.SSBD available. */ +XEN_CPUFEATURE(AMD_SSB_NO, 8*32+26) /* Hardware not vulnerable to SSB */ /* Intel-defined CPU features, CPUID level 0x00000007:0.edx, word 9 */ XEN_CPUFEATURE(AVX512_4VNNIW, 9*32+ 2) /*A AVX512 Neural Network Instructions */ -- 2.1.4 _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxxxxxxxxx https://lists.xenproject.org/mailman/listinfo/xen-devel
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