Re: [Xen-devel] [PATCH v4 06/44] x86emul: test for correct EVEX Disp8 scaling

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 14.11.18 at 15:42, <andrew.cooper3@xxxxxxxxxx> wrote:
> On 14/11/2018 14:17, Jan Beulich wrote:
>>> After re-reading the apparently relevant bits of Vol 1, 2 and 3, I'm
>>> still actually none the wiser as to which AVX512 feature bits mean what.
>> What feature bits are you talking about? The context above doesn't
>> refer to any, at least not directly.
> 
> I was referring to the AVX512 cpuid flags.
> 
> For example, it took me until writing that comment to realise that the
> VL feature bit behaved in the opposite way to how I expected it to
> behave.  (I.e. it allows you to encode EVEX instructions which don't
> refer to %zmm register).

Oh. AVX512, as its name says, implies 512-bit vectors. Shorter
forms are what they consider the Vector Length Extension (where
"extension" does _not_ refer to vector length, but to the wider
capabilities.) Some of the gcc issues I've run into appear to
relate to problems they have when AVX512F (i.e. without
AVX512VL) code wants to interact with code dealing with shorter
vectors. And that's despite some AVX512F insns themselves
having shorter operands (when element width widens or shrinks).

> Having said all of this, having searched about online, I think the
> Wikipedia AVX-512 page is probably the closes to what I was looking for,
> so perhaps us writing our own breakdown isn't the best idea.

Indeed. Plus the SDM insn pages look pretty correct in this particular
regard.

Jan



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