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Re: [Xen-devel] Interrupt injection with ISR set on Intel hardware

On Mon, Oct 22, 2018 at 03:33:07PM +0800, Chao Gao wrote:
> Hi, Roger, Andrew and Wei,
> Jan's patch
> (https://lists.xen.org/archives/html/xen-devel/2018-10/msg01031.html)
> fixs an issue in handling SVI. Currently, when dealing with EOI from guest, 
> the
> SVI was cleared. But the correct way is clearing the corresponding bit in VISR
> and then setting SVI to the highest index of bit set in VISR (please refer to
> SDM 29.1.4). If SVI is set to a value lower than the vector of the highest
> priority interrupt that is in service, the PPR virtualization (29.1.3) might
> set the VPPR to a lower value on VMEntry too. Thus an interrupt with same or
> lower priority, which should be blocked by VPPR, slips in.

AFAICT the patch is for the emulated lapic, and the issue we are
seeing here is with the hardware lapic.

> Could you apply Jan's patch and try to reproduce it again?

I've applied Jan's patch and I'm still able to reproduce the issue.

Thanks, Roger.

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