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Re: [Xen-devel] [PATCH v2] x86/boot: enable NMIs after traps init

  • To: Ross Philipson <ross.philipson@xxxxxxxxx>, Jason Andryuk <jandryuk@xxxxxxxxx>
  • From: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
  • Date: Wed, 24 Oct 2018 00:41:43 +0100
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  • Cc: sergey.dyasli@xxxxxxxxxx, Wei Liu <wei.liu2@xxxxxxxxxx>, eric chanudet <eric.chanudet@xxxxxxxxx>, Jan Beulich <jbeulich@xxxxxxxx>, xen-devel@xxxxxxxxxxxxx
  • Delivery-date: Tue, 23 Oct 2018 23:42:11 +0000
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
  • Openpgp: preference=signencrypt

On 23/10/2018 23:01, Ross Philipson wrote:
> On 10/23/2018 12:58 PM, Andrew Cooper wrote:
>> On 23/10/18 17:42, Ross Philipson wrote:
>>> On 10/23/2018 11:31 AM, Jason Andryuk wrote:
>>>> On Tue, Oct 23, 2018 at 10:46 AM Andrew Cooper
>>>> <andrew.cooper3@xxxxxxxxxx> wrote:
>>>>> On 23/10/18 15:01, Jason Andryuk wrote:
>>>>>> On Tue, Oct 23, 2018 at 7:15 AM Andrew Cooper 
>>>>>> <andrew.cooper3@xxxxxxxxxx> wrote:
>>>>>>> On 23/10/18 11:59, Sergey Dyasli wrote:
>>>>>>>> In certain scenarios, NMIs might be disabled during Xen boot process.
>>>>>>>> Such situation will cause alternative_instructions() to:
>>>>>>>>     panic("Timed out waiting for alternatives self-NMI to hit");
>>>>>>>> This bug was originally seen when using Tboot to boot Xen.
>>>>>>>> To prevent this from happening, enable NMIs during cpu_init() and
>>>>>>>> during __start_xen() for BSP.
>>>>>>>> Signed-off-by: Sergey Dyasli <sergey.dyasli@xxxxxxxxxx>
>>>>>>> Reviewed-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
>>>>>> FYI, Ross and Eric came up with a tboot patch recently added to OpenXT:
>>>>>> https://github.com/OpenXT/xenclient-oe/blob/master/recipes-openxt/tboot/tboot-1.9.6/0023-tboot-Unmask-NMI-potentially-masked-during-SENTER.patch
>>>>>> Using this Xen patch with the tboot one reverted works too.
>>>>>> Tested-by: Jason Andryuk <jandryuk@xxxxxxxxx>
>>>>> :(
>>>>> Can bugs like this please be reported upstream?  Given the observation
>>>>> of "Tboot hands off with NMIs disabled", the fix is very easy.
>>>> I'm not opposed to reporting upstream.  In this case, I at least
>>>> assumed it was something we did in our EFI & tboot combo.  An Ivy
>>>> Bridge legacy boot system with tboot & Xen worked fine.  For me, it
>>>> was only a newer Skylake (or Kaby Lake) machine that had issue when
>>>> booting our EFI & tboot combo.  So it wasn't clear that tboot always
>>>> left NMIs disabled.  Yes, we should have reported something upstream
>>>> as a heads up for other tboot/Xen users.
>>> According to the specs, NMIs and SMIs are disabled post launch on the BSP 
>>> and
>>> after AP wakeup is done. The TBOOT code explicitly re-enables SMIs but 
>>> currently
>>> not NMIs. Any IRET later on would have re-enabled them so it might explain 
>>> how
>>> they incidentally get re-enabled in certain configurations.
>>> Personally I think the fix to re-enable them in TBOOT should go upstream.
>> Which spec?  Can it be changed/improved?
>> I accept this might be what it currently says, but enabling NMIs before
>> the OS is capable of handling them is only going to cause sad users on
>> anything but a completely idle system.
> Sorry I should have been clearer. The Intel SDM states that various GETSEC 
> leaf
> functions leave the BSP or APs with both SMIs and NMIs disabled. It does not 
> say
> anything about where/when they should be re-enabled. It is the TBOOT
> implementation that (presumably though it is not documented) decided to
> re-enable SMIs and not NMIs.

Oh - that's nice.  I wonder what the reason for that behaviour is? ;)

>> x86 is a gnarley architecture when it comes to this level of detail.  It
>> is not possible for a kernel to be a mode transition (real => protected,
>> or into long mode) and handle interrupts safely, because we can't
>> atomically set the mode and change the layout/position of the IDT.
>> We can at least avoid taking #MC when it is definitely unsafe to do so,
>> by not having CR4.MCE set.  An #MC at that point will be terminal to the
>> system, but you've got hardware problems at that point and all bets were
>> off anyway.  (Also, for those not keeping score on L1 Terminal Fault and
>> disabling hyperthreads threads, if any single one of your hyperthreads
>> has CR4.MCE clear, e.g. because your in the middle of booting it, an #MC
>> is fatal to the system.)
>> For NMI's the only way of guaranteeing that one doesn't arrive until the
>> IDT is set up properly is to leave the NMI shadow active until the OS
>> explicitly decided that it is safe.
>> While some might be viewed as a bug in tboot, I view it as a feature
> Hmm that is an interesting perspective and I see your point. We will have to
> think about this with respect to where we try to re-enable NMIs. On the other
> side of this though, how long is it safe to leave NMIs disabled before it 
> causes
> a problem on the platform depending on what the NMIs might be doing? I believe
> incoming NMIs are being pended in this state - that is clearly stated at least
> on AMD when clearing/setting GIF.

NMIs are handled as edge triggered.

As soon as one NMI is accepted, the NMI shadow is asserted until the
following IRET instruction.  (Faults for this IRET drop the shadow
before logically finishing the NMI handler, which is how we can end up
in the corner case of re-entrant NMIs - an issue which I still haven't
fixed in Xen yet.)

One single NMI can be held pending when one is in service, which will be
delivered as soon as the NMI shadow clears.  (It is possible from the
point of view of the NMI handler to observe a livelock on the underlying
code if one NMI gets delivered during the running of the running of the
NMI handler.  It turns our that Skylake hardware can easily spend 200ns
in SMI context on a read from port 0x61, which doesn't combine well with
a retired-instructions perfcounter serving as a watchdog.)

As for "how long is it safe to leave disabled", that still fairly easy
to answer.  What would you miss out on by not handling NMIs immediately?

The kernel itself won't set up sources of NMIs which it isn't capable of
handling, because that would be silly.  Therefore, we don't have IPIs or
perf counters configured with a delivery type of NMI.

Realistically, that means that arriving NMIs during this period are of
the unexpected variety, so most likely a PCI SERR/IOCK or other
interrupts raised by the system.  These really are safe to defer for the
milliseconds it takes to switch mode and get interrupt handling working

>> which should be retained.  How late can late launches occur in practice?
> Theoretically at any point SMX mode can be entered/left/entered/etc - at least
> that is how I understand it on Intel platforms.

Right, which can be after PCI devices are starting to be used in anger.


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