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[Xen-devel] Ping: [PATCH v3 0/4] x86/HVM: implement memory read caching

>>> On 25.09.18 at 16:14, <JBeulich@xxxxxxxx> wrote:
> Emulation requiring device model assistance uses a form of instruction
> re-execution, assuming that the second (and any further) pass takes
> exactly the same path. This is a valid assumption as far as use of CPU
> registers goes (as those can't change without any other instruction
> executing in between), but is wrong for memory accesses. In particular
> it has been observed that Windows might page out buffers underneath
> an instruction currently under emulation (hitting between two passes).
> If the first pass translated a linear address successfully, any subsequent
> pass needs to do so too, yielding the exact same translation.
> Introduce a cache (used just by guest page table accesses for now, i.e.
> a form of "paging structure cache") to make sure above described
> assumption holds. This is a very simplistic implementation for now: Only
> exact matches are satisfied (no overlaps or partial reads or anything).
> There's also some seemingly unrelated cleanup here which was found
> desirable on the way.
> 1: x86/mm: add optional cache to GLA->GFN translation
> 2: x86/mm: use optional cache in guest_walk_tables()
> 3: x86/HVM: implement memory read caching
> 4: x86/HVM: prefill cache with PDPTEs when possible
> As for v2, I'm omitting "VMX: correct PDPTE load checks" from v3, as I
> can't currently find enough time to carry out the requested further
> rework.

Andrew, George?


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