Re: [Xen-devel] [PATCH v6 01/14] iommu: introduce the concept of BFN...

["Tian, Kevin" <kevin.tian@xxxxxxxxx>]

> From: Jan Beulich [mailto:JBeulich@xxxxxxxx]
> Sent: Tuesday, September 4, 2018 5:08 PM
> 
> >>> On 04.09.18 at 10:49, <Paul.Durrant@xxxxxxxxxx> wrote:
> >>  -----Original Message-----
> >> From: Jan Beulich [mailto:JBeulich@xxxxxxxx]
> >> Sent: 04 September 2018 09:47
> >> To: Kevin Tian <kevin.tian@xxxxxxxxx>
> >> Cc: Suravee Suthikulpanit <suravee.suthikulpanit@xxxxxxx>; Julien
> Grall
> >> <julien.grall@xxxxxxx>; Paul Durrant <Paul.Durrant@xxxxxxxxxx>;
> Stefano
> >> Stabellini <sstabellini@xxxxxxxxxx>; xen-devel <xen-
> >> devel@xxxxxxxxxxxxxxxxxxxx>
> >> Subject: Re: [Xen-devel] [PATCH v6 01/14] iommu: introduce the concept
> of
> >> BFN...
> >>
> >> >>> On 04.09.18 at 10:37, <kevin.tian@xxxxxxxxx> wrote:
> >> >>  From: Jan Beulich [mailto:JBeulich@xxxxxxxx]
> >> >> Sent: Tuesday, September 4, 2018 4:33 PM
> >> >> >
> >> >> > bus address is commonly used along with physical/virtual address,
> to
> >> >> > represent different views between devices and CPU. From that
> angle
> >> >> > I think BFN is a clear term in this context. btw it is not necessary 
> >> >> > to
> >> >> > differentiate GBFN and MBFN since there is only one BFN view per
> >> >> > device.
> >> >>
> >> >> Sure, but you neglect the presence of one or more IOMMUs when
> >> >> you say "between devices and CPU". There addresses prior to and
> >> >> after IOMMU translation are distinct, and while the one before the
> >> >> translation matches the device view, the one after translation does
> >> >> not necessarily match the CPU view. Hence there are two "bus"
> >> >> frame numbers here - one representing the device view, and the
> >> >> other representing the IOMMU (output) view.
> >> >>
> >> >
> >> > I didn't get. the output address from IOMMU is the one sent to
> >> > memory controller, same as the one sent from CPU.
> >>
> >> That's on present x86 systems, but aiui not in the general case. The
> >> terminology to be used in Xen should fit the general case though.
> >
> > So your concern is cascaded IOMMUs?
> 
> Not primarily. My concern are systems with an I/O address space
> (behind the IOMMU) distinct from the CPU address space. Iirc at
> least Alpha is/was that way.
> 

Then Paul please documents clearly that this bus address refers to
the input side of IOMMU. :-)

Thanks
Kevin

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