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Re: [Xen-devel] [PATCH v2 05/10] x86/SVM: Add AVIC vmexit handlers


  • To: "Natarajan, Janakarajan" <jnataraj@xxxxxxx>, Jan Beulich <JBeulich@xxxxxxxx>, Janakarajan Natarajan <Janakarajan.Natarajan@xxxxxxx>
  • From: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
  • Date: Wed, 30 May 2018 00:33:42 +0100
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  • Cc: Kevin Tian <kevin.tian@xxxxxxxxx>, Stefano Stabellini <sstabellini@xxxxxxxxxx>, Wei Liu <wei.liu2@xxxxxxxxxx>, Suravee Suthikulpanit <suravee.suthikulpanit@xxxxxxx>, George Dunlap <George.Dunlap@xxxxxxxxxxxxx>, Tim Deegan <tim@xxxxxxx>, Ian Jackson <Ian.Jackson@xxxxxxxxxxxxx>, xen-devel@xxxxxxxxxxxxx, Julien Grall <julien.grall@xxxxxxx>, Jun Nakajima <jun.nakajima@xxxxxxxxx>, Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx>
  • Delivery-date: Tue, 29 May 2018 23:34:00 +0000
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
  • Openpgp: preference=signencrypt

>>> +        {
>>> +            gprintk(XENLOG_ERR, "%s: Failed to handle trap write
>>> (%#x)\n",
>>> +                    __func__, offset);
>>> +            domain_crash(curr->domain);
>>> +        }
>>> +    }
>>> +    else
>>> +        /* Handling AVIC Fault (intercept before the access). */
>>> +        hvm_emulate_one_vm_event(EMUL_KIND_NORMAL, TRAP_invalid_op,
>>> +                                 X86_EVENT_NO_EC);
>> What's the rationale behind having chosen this function? I don't
>> think it is
>> supposed to be called from outside the VM event code.
>
> We wanted to handle the AVIC fault by emulating the instruction
> causing it.
> Would this be better suited ?

Almost.

The purpose of the validate function is to fix an inherent race
condition which occurs with a vmexit.

After a vmexit, rereading the instruction for emulation is inherently
racy, and a malicious VM could rewrite the instruction stream while the
vmexit is occuring.  As a result, we provide a validate function to
check that the instruction decoded matches one which plausibly broke for
emulation here.

Therefore, you want a validate function which checks that the
instruction has a memory operand, and that it falls within the 4k region
which maps the APIC registers.

~Andrew

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