Re: [Xen-devel] [PATCH v4 1/7] xen/arm: Read the dcache line size from CTR register

[Julien Grall <julien.grall@xxxxxxx>]

Hi Stefano,

On 02/03/18 19:06, Stefano Stabellini wrote:
> diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h
> index d948250..ce18f0c 100644
> --- a/xen/include/asm-arm/page.h
> +++ b/xen/include/asm-arm/page.h
> @@ -134,7 +134,7 @@
>   /* Architectural minimum cacheline size is 4 32-bit words. */
>   #define MIN_CACHELINE_BYTES 16
>   /* Actual cacheline size on the boot CPU. */
You probably want to update that comment either in this patch or #7.

With that:

Reviewed-by: Julien Grall <julien.grall@xxxxxxx>

Cheers,

--
Julien Grall

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