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[Xen-devel] [RFC PATCH 00/10] arm64: Mediate access to GICv3 sysregs at EL2

From: Manish Jaggi <manish.jaggi@xxxxxxxxxx>

This patchset is a Xen port of Marc's patchset.
arm64: KVM: Mediate access to GICv3 sysregs at EL2 [1]

The current RFC patchset is a subset of [1], as it handleing only Group1 traps
as a PoC. Most of the trap code is added in vsysreg.c. Trap handler function is 
independent of the usual guest trap handling code. 
Looking for feedback on this approach.  

The errata has been validated on Cavium ThunderX platform.

Steps to reporduce the errata
- Boot Xen with 2 cores.
- Disable group1 interrupts in domU kernel
- start domU, the kill and start again.
One of the Xen core would hang.

Code in this patchset fixes this issue.

[1] https://lists.cs.columbia.edu/pipermail/kvmarm/2017-June/026029.html

Manish Jaggi (10):
  arm64: Add hook to handle guest GICv3 sysreg accesses
  arm64: Add ICV_BPR1_EL1 handler
  arm64: Add ICV_IGRPEN1_EL1 handler
  arm64: Add accessors for the ICH_APxRn_EL2 registers
  arm64: Expose gicv3_ich_read/write_lr
  arm64: Add ICV_IAR1_EL1 handler
  arm64: Add ICV_EOIR1_EL1 handler
  arm64: Add a handler for ICV_HPPIR1_EL1
  arm64: Enable Trapping of Group1 registers which is controlled by
    command line

 xen/arch/arm/Kconfig                |   9 +
 xen/arch/arm/arm64/vsysreg.c        | 564 ++++++++++++++++++++++++++++++++++++
 xen/arch/arm/gic-v3.c               |  21 +-
 xen/arch/arm/traps.c                |  11 +
 xen/include/asm-arm/arm64/sysregs.h |   5 +
 xen/include/asm-arm/arm64/traps.h   |   2 +
 xen/include/asm-arm/gic.h           |   1 +
 xen/include/asm-arm/gic_v3.h        |   7 +
 xen/include/asm-arm/gic_v3_defs.h   |  30 ++
 9 files changed, 649 insertions(+), 1 deletion(-)
 create mode 100644 xen/include/asm-arm/gic_v3.h


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