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Re: [Xen-devel] [PATCH v6.5 15/26] x86/feature: Definitions for Indirect Branch Controls

On Thu, Jan 04, 2018 at 12:15:44AM +0000, Andrew Cooper wrote:
> Contemporary processors are gaining Indirect Branch Controls via microcode
> updates.  Intel are introducing one bit to indicate IBRS and IBPB support, and
> a second bit for STIBP.  AMD are introducing IPBP only, so enumerate it with a
> separate bit.
> Furthermore, depending on compiler and microcode availability, we may want to
> run Xen with IBRS set, or clear.
> To use these facilities, we synthesise separate IBRS and IBPB bits for
> internal use.  A lot of infrastructure is required before these features are
> safe to offer to guests.
> Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
> ---
> v4:
>  * Update for AMD, drop acks/reviews.
> ---
>  tools/libxl/libxl_cpuid.c                   |  3 +++
>  tools/misc/xen-cpuid.c                      | 12 ++++++++++--

Acked-by: Wei Liu <wei.liu2@xxxxxxxxxx>

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