Re: [Xen-devel] [PATCH] x86emul: correct EVEX register extension bit handling for non-64-bit modes

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 05.09.17 at 15:07, <andrew.cooper3@xxxxxxxxxx> wrote:
> On 10/07/17 08:25, Jan Beulich wrote:
>> While these are latent issues only for now, correct them right away:
>> - EVEX.V' (called RX in our code) needs to uniformly be 1,
>> - EXEX.R' (called R in our code) is uniformly being ignored.
>>
>> Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
> 
> Those changes do match table 2-40 in the manual, but what about other cases?
> 
> EVEX.B is uniformly ignored outside of 64bit as well.

Which is being taken care of by

                        /* Operand size fixed at 4 (no override via W bit). */
                        op_bytes = 4;
                        vex.b = 1;

followed a few lines later by

                        opcode = X86EMUL_OPC_EVEX_;
                        evex.raw[0] = vex.raw[0];
                        evex.raw[1] = vex.raw[1];
                        evex.raw[2] = insn_fetch_type(uint8_t);

.

> What about the opcode independent cases?  We should check that the two
> MBZ bits (currently an anonymous bitfield) are zero, and the MBS bit
> (currently evex.evex) is set.

Yes, I could add these here right away instead of deferring until
later.

Jan


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