Re: [Xen-devel] [PATCH 1/4] arm: processor: rename iss to res0 in hsr_cond union

[Julien Grall <julien.grall@xxxxxxx>]

Hi,

On 07/28/2017 08:43 PM, Volodymyr Babchuk wrote:
> Name "iss" in this case was used not exactly correctly, because this
> is only part of HSR.ISS field. ARM refence manual denotes this
s/refence/reference/

> part of ISS as RES0 when it describes encoding for conditional
> exceptions.
When you mention the ARM ARM, please mention the version of the manual 
and paragraph. At the moment looking at the ARM v7 (ARM DDI 0406C.c) 
B3.13.6, this is not true.
Cheers,

> Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@xxxxxxxx>
> ---
>   xen/include/asm-arm/processor.h | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
> index 855ded1..f640d54 100644
> --- a/xen/include/asm-arm/processor.h
> +++ b/xen/include/asm-arm/processor.h
> @@ -434,7 +434,7 @@ union hsr {
>   
>       /* Common to all conditional exception classes (0x0N, except 0x00). */
>       struct hsr_cond {
> -        unsigned long iss:20;  /* Instruction Specific Syndrome */
> +        unsigned long res0:20;  /* Reserved */
>           unsigned long cc:4;    /* Condition Code */
>           unsigned long ccvalid:1;/* CC Valid */
>           unsigned long len:1;   /* Instruction length */
--
Julien Grall

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