Re: [Xen-devel] [PATCH v2] x86/vpmu_intel: Fix hypervisor crash by masking PC bit in MSR_P6_EVNTSEL

[Andrew Cooper <andrew.cooper3@xxxxxxxxxx>]

On 26/04/17 19:11, Mohit Gambhir wrote:
> Setting Pin Control (PC) bit (19) in MSR_P6_EVNTSEL results in a General
> Protection Fault and thus results in a hypervisor crash. This patch fixes the
> crash by masking PC bit and returning an error in case any guest tries to 
> write
> to it.
>
> Signed-off-by: Mohit Gambhir <mohit.gambhir@xxxxxxxxxx>

Out of interest, which hardware has this been observed on?

~Andrew

> ---
> v2 of this patch takes a different approach to fixing the hypervisor crash.
> As stated in the commit message v2 masks PC flag control bit unlike v1 that 
> used wrmsr_safe while writing to the MSR. v1 posed a complication in returning
> the error to the HVM guests.
>
> With this approach the writes to PC bits are protected for both native MSR 
> writes and VMX data structure writes (for HVM guests)
> ---
>  xen/arch/x86/cpu/vpmu_intel.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.c
> index 3f0322c..6d768cb 100644
> --- a/xen/arch/x86/cpu/vpmu_intel.c
> +++ b/xen/arch/x86/cpu/vpmu_intel.c
> @@ -76,12 +76,13 @@ static bool_t __read_mostly full_width_write;
>  #define FIXED_CTR_CTRL_ANYTHREAD_MASK 0x4
>  
>  #define ARCH_CNTR_ENABLED   (1ULL << 22)
> +#define ARCH_CNTR_PIN_CONTROL (1ULL << 19)
>  
>  /* Number of general-purpose and fixed performance counters */
>  static unsigned int __read_mostly arch_pmc_cnt, fixed_pmc_cnt;
>  
>  /* Masks used for testing whether and MSR is valid */
> -#define ARCH_CTRL_MASK  (~((1ull << 32) - 1) | (1ull << 21))
> +#define ARCH_CTRL_MASK  (~((1ull << 32) - 1) | (1ull << 21) | 
> ARCH_CNTR_PIN_CONTROL)
>  static uint64_t __read_mostly fixed_ctrl_mask, fixed_counters_mask;
>  static uint64_t __read_mostly global_ovf_ctrl_mask, global_ctrl_mask;
>  


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