Re: [Xen-devel] PVH Dom0 Intel IOMMU issues

[Roger Pau Monné <roger.pau@xxxxxxxxxx>]

On Tue, Apr 18, 2017 at 02:48:31AM -0600, Jan Beulich wrote:
> >>> On 18.04.17 at 09:34, <roger.pau@xxxxxxxxxx> wrote:
> > (XEN) Before DMA_GCMD_TE
> > (
> > 
> > The hang seems to happen when writing DMA_GCMD_TE to the global command
> > register, which enables the DMA remapping. After that the box is completely
> > unresponsive, not even the watchdog is working.
> 
> How sure are you that this is pre-Haswell specific vs e.g. chipset or
> firmware (think of RMRRs [or their lack] for the latter) dependent?
> Iirc Elena's command line specifiable RMRR patch series was
> motivated by similar behavior she had observed on some system.

This is mostly from trial/error. I don't think it's strictly CPU related, but
rather chipset related (ie: chipsets that come with pre-haswell CPUs).

Elena IIRC was at least getting IOMMU faults, which I don't even get in my
case, and I think that's the issue itself.

> Another odd aspect is - why would IOMMU enabling cause the hang
> only when intending to use a PVH Dom0? The IOMMU is being
> enabled in either case, which again might point at differences in use
> of memory.

Not sure, for PVH Dom0 the IOMMU is enabled quite early in the domain build
process (before populating the domain p2m), which seems to be fine on other
systems.

I've done that (initializing the IOMMU so early) to avoid having to iterate
over the list of domain pages afterwards when the IOMMU is initialized with the
p2m already populated.

FWIW, moving the iommu_hwdom_init call to the end of the PVH Dom0 build process
doesn't solve the issue. I've also tried with and without shared pt, and the
result is the same.

Roger.

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