Re: [Xen-devel] [PATCH] X86/VPMU: mask off uncore overflow bit on xeon phi knights landing

[Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx>]

On 12/08/2016 10:17 PM, Luwei Kang wrote:
> IA32_PERF_GLOBAL_STATUS.OvfUncore (MSR 38EH, bit[61]) is always 0 and
> writing 1 to IA32_PERF_GLOBAL_OVF_CTRL.ClrOvfUncore (MSR 390H, bit[61])
> signals #GP.
> Reference "Intel Xeon Phi Procssor x200 Product Family", document
> number 334646-008.
>
> Signed-off-by: Luwei Kang <luwei.kang@xxxxxxxxx>
> ---
>  xen/arch/x86/cpu/vpmu_intel.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.c
> index e8049ed..0be78ff 100644
> --- a/xen/arch/x86/cpu/vpmu_intel.c
> +++ b/xen/arch/x86/cpu/vpmu_intel.c
> @@ -1058,11 +1058,17 @@ int __init core2_vpmu_init(void)
>                               (((1ULL << fixed_pmc_cnt) - 1) << 32) |
>                               ((1ULL << arch_pmc_cnt) - 1));
>      if ( version > 2 )
> +    {
>          /*
>           * Even though we don't support Uncore counters guests should be
>           * able to clear all available overflows.
>           */
>          global_ovf_ctrl_mask &= ~(1ULL << 61);
> +        /* Knight Landing doesn't support overflow bit on uncore counters */
> +        if ( current_cpu_data.x86_model == 0x57 )
> +            global_ovf_ctrl_mask |= (1ULL << 61);
> +
> +    }
>

I think these types of model-specific changes (or errata) should be done
in check_pmc_quirk(). And is_pmc_quirk (along with handle_pmc_quirk())
should be renamed to something more specific to that particular problem.
Maybe pmc_underflow_quirk?

-boris


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