Re: [Xen-devel] [for-4.8][PATCH] xen/arm64: Add missing synchronization barrier in invalidate_cache

[Stefano Stabellini <sstabellini@xxxxxxxxxx>]

On Wed, 21 Sep 2016, Konrad Rzeszutek Wilk wrote:
> On Wed, Sep 21, 2016 at 03:52:12PM +0100, Julien Grall wrote:
> > The invalidation of the instructions cache requires barriers to ensure
> > the completion of the invalidation before continuing (see B2.3.4 in ARM
> > DDI 0487A.j).
> > 
> > This was overlooked in commit fb9d877 "xen/arm64: Add an helper to
> > invalidate all instruction caches".
> > 
> > Signed-off-by: Julien Grall <julien.grall@xxxxxxx>
> 
> Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@xxxxxxxxxx>

Reviewed-by: Stefano Stabellini <sstabellini@xxxxxxxxxx>

and committed

> 
> > ---
> >  xen/include/asm-arm/arm64/page.h | 2 ++
> >  1 file changed, 2 insertions(+)
> > 
> > diff --git a/xen/include/asm-arm/arm64/page.h 
> > b/xen/include/asm-arm/arm64/page.h
> > index 79ef7bd..23d7781 100644
> > --- a/xen/include/asm-arm/arm64/page.h
> > +++ b/xen/include/asm-arm/arm64/page.h
> > @@ -33,6 +33,8 @@ static inline void write_pte(lpae_t *p, lpae_t pte)
> >  static inline void invalidate_icache(void)
> >  {
> >      asm volatile ("ic ialluis");
> > +    dsb(ish);               /* Ensure completion of the flush I-cache */
> > +    isb();
> >  }
> >  
> >  /*
> > -- 
> > 1.9.1
> > 
> 

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