[Xen-devel] [PATCH] x86/levelling: Fix breakage on older Intel boxes from c/s 08e7738

[Andrew Cooper <andrew.cooper3@xxxxxxxxxx>]

cpufeat_mask() yields an unsigned integer constant.  As a result, taking its
complement causes zero extention rather than sign extention.

The result is that, when a guest OS has OXSAVE disabled, all features in 1d
are hidden from native CPUID.  Amongst other things, this causes the early
code in Linux to find no LAPIC, but for everything to appear fine later when
userspace is up and running.

Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
---
CC: Jan Beulich <JBeulich@xxxxxxxx>

I wonder whether a better fix might be to put an explicit (int) cast in
cpufeat_mask() to yield an signed constant?
---
 xen/arch/x86/cpu/intel.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c
index a9355cbf..7b60aaa 100644
--- a/xen/arch/x86/cpu/intel.c
+++ b/xen/arch/x86/cpu/intel.c
@@ -192,7 +192,7 @@ static void intel_ctxt_switch_levelling(const struct vcpu 
*next)
                 */
                if (next && is_pv_vcpu(next) && !is_idle_vcpu(next) &&
                    !(next->arch.pv_vcpu.ctrlreg[4] & X86_CR4_OSXSAVE))
-                       val &= ~cpufeat_mask(X86_FEATURE_OSXSAVE);
+                       val &= ~(uint64_t)cpufeat_mask(X86_FEATURE_OSXSAVE);
 
                if (unlikely(these_masks->_1cd != val)) {
                        wrmsrl(msr_basic, val);
-- 
2.1.4


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