Re: [Xen-devel] XSA 154 and ISA region (640K -> 1MB) WB cache instead of UC

[One Thousand Gnomes <gnomes@xxxxxxxxxxxxxxxxxxx>]

On Thu, 18 Aug 2016 05:12:54 -0600
"Jan Beulich" <JBeulich@xxxxxxxx> wrote:

> >>> On 18.08.16 at 12:16, <andrew.cooper3@xxxxxxxxxx> wrote:  
> > On 18/08/16 11:06, Jan Beulich wrote:  
> >>>>> On 17.08.16 at 22:32, <konrad.wilk@xxxxxxxxxx> wrote:  
> >>>    Looking at the kernel it assumes that WB is ok for 640KB->1MB.
> >>>    The comment says:
> >>>    " /* Low ISA region is always mapped WB in page table. No need to 
> >>> track   
> > *"  
> >> As per above it's not clear to me what this comment is backed by.  
> > 
> > This states what is in the pagetables.  Not the combined result with MTRRs.
> > 
> > WB in the pagetables and WC/UB in the MTRRs is a legal combination which
> > functions correctly.  
> 
> True, but then again - haven't I been told multiple times that Linux
> nowadays prefers to run without using MTRRs?

The BIOS sets up the fixed MTRR registers for the 640K-1MB window. Those
are separate to the variable range MTRR registers used for main memory
with specific mappings for segments A000 to BFFF then C000-C7FF /
C800-CFFF / etc up to FFFF.

Alan

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