Re: [Xen-devel] [PATCH 1/2] AMD/VPMU: 0xc0010000 - 0xc001007 MSRs are in PMU range

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 08.08.16 at 16:06, <boris.ostrovsky@xxxxxxxxxx> wrote:
> On 08/08/2016 09:53 AM, Jan Beulich wrote:
>>>>> On 08.08.16 at 15:41, <boris.ostrovsky@xxxxxxxxxx> wrote:
>>> --- a/xen/arch/x86/traps.c
>>> +++ b/xen/arch/x86/traps.c
>>> @@ -2903,6 +2903,7 @@ static int emulate_privileged_op(struct cpu_user_regs 
> *regs)
>>>              {
>>>                  vpmu_msr = 1;
>>>          case MSR_AMD_FAM15H_EVNTSEL0...MSR_AMD_FAM15H_PERFCTR5:
>>> +        case MSR_K7_EVNTSEL0...MSR_K7_PERFCTR3:
>>>                  if ( vpmu_msr || (boot_cpu_data.x86_vendor == 
> X86_VENDOR_AMD) )
>>>                  {
>>>                      if ( (vpmu_mode & XENPMU_MODE_ALL) &&
>>> @@ -3030,6 +3031,7 @@ static int emulate_privileged_op(struct cpu_user_regs 
> *regs)
>>>              {
>>>                  vpmu_msr = 1;
>>>          case MSR_AMD_FAM15H_EVNTSEL0...MSR_AMD_FAM15H_PERFCTR5:
>>> +        case MSR_K7_EVNTSEL0...MSR_K7_PERFCTR3:
>>>                  if ( vpmu_msr || (boot_cpu_data.x86_vendor == 
> X86_VENDOR_AMD) )
>>>                  {
>>>  
>> And all the logic in vpmu_amd.c is already in suitable shape? Namely
>> I'm wondering whether CTRL_RSVD_MASK indeed applies uniformly
>> to both the pre-Fam15 and Fam15+ MSRs.
> 
> The reserved bits look the same on all supported families --- bits
> 63:42, 39:36, 21 and 19. Except apparently on family 12h bit 19 is MBZ.

Isn't MBZ == reserved for all practical purposes? In any event the
patch is fine then afaic.

Jan


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